DFT IP Generator
Multidimensional DFT IP Generator for FPGA Platforms
FREE-DOWNLOAD [PDF] CL Yu, K Irick, C Chakrabarti… – research Transactions on …, 2011
This setting is for the MD DFT function verification. 3200 MB/s. To achieve a much higher
performance, the proposed architecture is currently being ported onto the Xilinx ML605 FPGA
board , which is equipped with a Virtex-6 LX240T FPGA and a DDR3–800 SDRAM Phys.