MULTIPLIER ARCHITECTURE-VLSI PROJECTS


High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics
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A NXN bit parallel overlay multiplier architecture is designed for high speed DSP operations. The architecture is based on the vertical and crosswise algorithm of ancient Indian Vedic Mathematics. In the proposed architecture grouping of the bits 4 at a time is done for both the

A Digital Multiplier Architecture using UrdhvaTiryakbhyam Sutra of Vedic Mathematics
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Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in early twentieth century. Vedic mathematics is mainly based on sixteen principles or word-formulae which are termed as Sutras. We discusses a possible

A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics.
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In this paper new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is based on generating all partial products and their sums in one step. The design implementation is

Implementation of a pipelined modular multiplier architecture for GF (p) elliptic curve cryptography computation
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This paper reflects the achievement of improved results in terms of cost for Pipelined Crypto Modular Multiplier Architecture when compared with its earlier versions of Parallel Crypto Architecture . The improved pipelined modular multiplier is implemented on Field

An RNS architecture of an Fp elliptic curve point multiplier .
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An Elliptic Curve Point Multiplier (ECPM) is the main part of all Elliptic Curve Cryptography (ECC) systems and its performance is decisive for the performance of the overall cryptosystem. A VLSI Residue Number System (RNS) architecture of an ECPM is presented

Pipelined Vedic-Array Multiplier Architecture
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In this paper, pipelined Vedic-Array multiplier architecture is proposed. The most significant aspect of the proposed multiplier architecture method is that, the developed multiplier architecture is designed based on the Vedic and Array methods of multiplier architecture

An advancement in the N N Multiplier Architecture Realization via the Ancient Indian Vedic Mathematics
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Multiplication is an crucial unfussy, basic function in arithmetic procedures and Vedic mathematics is a endowment prearranged for the paramount of human race, due to the capability it bestows for quicker intellectual computation. This paper presents the

VLSI architecture of parallel multiplier accumulator based on radix-2 modified booth algorithm
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A new architecture of multiplier -and accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in

Low Power 32 32 bit multiplier architecture based on Vedic mathematics using virtex 7 low power device
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In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per this proposed architecture , for two 32-bit numbers; the multiplier and

Area and power efficient VLSI architecture for FIR filter using asynchronous multiplier
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The FIR filter is commonly used in many applications such as communication or multimedia signal processing. In the existing method, the design of FIR filter structure, based on synchronous multiplier such as Wallace tree multiplier design is considered. It leads to fewer

A New Hybrid 16-Bit x 16-Bit Multiplier Architecture by m: 2 and m: 3 Compressors
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Compressors are mostly used in multipliers to reduce partial products in a parallel manner. Firstly, this paper draw a comparison between the conventional m: 2 and m: 3 compressors. Secondly, a new hybrid 16-bit 16-bit multiplier is proposed in this paper with the aim of

Radix-4/-8 Dual Encoder Block for Multiplier Architecture using GDI Technique
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A hybrid radix-4/-8 multiplier is proposed for portable multimedia applications that demand high speed and low energy operation. Depending on the input pattern, the multiplier operates in the radix-8 mode in 56% of the input cases for low power, but reverts to the radix

A Low Power Reversible Braun Array Multiplier Architecture using KTR Gate
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The current digital era is more tempted towards the Reversible logic design because of its low power consumption. Multiplication is the basic building block for several DSP processors, Image processing etc. In Digital Signal Processors the computing complexities

A Modified Architecture Of Multiplier And Accumulator Using Spurious Power Suppression Technique
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Accumulator (MAC) unit is at most requirement of todays VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture , Radix-4 Modified Booth Encoding (MBE) is used to produce the

Implementation of New VLSI Architecture of Multiplier and Accumulator using Carry Save Adder
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In this paper, we proposed a new architecture of multiplier -and-accumulator (MAC) for high- speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has

A New VLSI Architecture of Parallel Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm
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In this paper, we proposed a new architecture of multiplier -and-accumulator (MAC) for high- speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has

VHDL Implementation of Logic BIST (Built In Self Test) Architecture for Multiplier Circuit for High Test Coverage in VLSI Chips
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Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of integrated circuit technology. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant

Modified Booth Multiplier Architecture Using New (1 11) Adder
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In this paper an alternate implementation of the modified Booth algorithm is presented where groups of the partial product terms are summed using parallel prefix adders proposed by Harris et al. Comparative analysis of these adders in terms of power, delay and LUTs is

Analog VLSI Implementation of Noval Hybrid Neural Network Multiplier Architecture
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Neural networks are suitable to resolve problems where conventional resolution methods fail. The multipliers form a basic and important block in realising a neural network and this is commonly known as Synapse . Their roles are to multiply an input current with trained

An Efficient Single Precision Floating Point Multiplier Architecture based on Classical Recoding Algorithm
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Abstract Background: Floating Point (FP) multiplication has found its importance in many microprocessors but it is very difficult to implement on FPGA because of its complicated internal computation. Methods: We investigate partial product (PP) reduced FP multiplication



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