Virtuoso Multi-Mode Simulation MMSIM
Comprehensive design and verification with the industry’s leading simulators Virtuoso Multi-Mode Simulation offers a complete verification solution for silicon realization
• Virtuoso AMS Designer Verification Option for advanced SoC verification These simulators support a common syntax, use common device model equations, and are fully integrated into the Virtuoso Analog Design Environment and the Cadence Incisive® design and verification flow. The complementary feature sets of these simulators delivers improved productivity and facilitates adoption as designs move through the architecture, implementation, and verification stages—and as simulation needs
• Uses silicon-accurate device models across all simulators that are universally supported by all foundry process design kits (PDKs)
• Supports shared syntax and abstractions across all engines and minimizes translation when moving among design domains
• Features tight integration with the Virtuoso Analog Design Environment— with common use model, crossprobing, and backannotation capabilities
• Features tight integration into the Incisive Logic Design Environment— with common-use model, debugging, waveform viewing, and language support
• Provides a proven, comprehensive suite of high-precision analyses with a simple use model, delivering accurate results
• Offers post-layout simulation and signoff analysis to ensure first-pass silicon realization success Scalability in performance
• Delivers simulation performance for complex and large analog/RF, custom digital, and mixed-signal designs
• Offers high-performance parallel simulation by harnessing the power of clusters of multi-core compute platforms to deliver peak performance Productivity
• Provides high-performance and high-capacity transistor-level verification of a wide range of analog, custom-digital, and mixed-signal designs
• Offers flexible and reliable abstraction for analog and digital-centric mixedsignal design flows, delivering faster simulation turnaround time Features
Silicon-accurate modeling All Virtuoso Multi-Mode Simulation engines use the same device model equations, eliminating model correlation issues and enabling faster convergence on simulation results. Common equations also ensure that new device model updates are available with all the simulators at the same time. Greater performance and capacity Virtuoso Multi-Mode Simulation engines provide the best combination of performance and capacity without sacrificing accuracy.
Language and netlist support
Virtuoso Multi-Mode Simulation supports a variety of abstraction methods. It is compatible with most commonly used SPICE input decks for both pre- and post-layout. It can natively read Spectre, SPICE, and Verilog-A netlist formats and device models. It also supports standard language inputs in Verilog-AMS, VHDL-AMS, Verilog-A, Verilog, and VHDL formats. Post-layout simulation Verification for post-layout designs has become increasingly important with advanced nanometer processes. For larger designs such as analog subsystems and full chips, the post-layout parasitics data is growing exponentially at 65nm and below.
Virtuoso Multi-Mode Simulation offers a flexible solution for SPICE-level postlayout simulations of complex and large designs—with tens of thousands of circuit devices dominated by parasitics. Virtuoso Multi-Mode Simulation meets the SoC design verification challenge with a combination of unique hierarchical parasitic stitching techniques and an accurate frequency-based parasitic reduction algorithm. This approach delivers the performance and capacity for post-layout verification of large designs. It also provides an optimized power net simulation technique and methodology for analysis of effects such as IR drop, signal integrity, timing, and substrate degradation.
As gate oxide thickness and dimensions of scale shrink in IC design, reliability problems occur and need to be considered early in the design process. Some of the more problematic issues include negative bias temperature instability (NBTI) and hot carrier injection (HCI). These can lead to problems such as performance degradation, burn-in yield loss, leakage current increase leading to increased power consumption, and even functional failure of ICs. Virtuoso Multi-Mode Simulation provides a full-chip reliability simulation and analysis solution, enabling designers to consider reliability effects in the early stages of design and ensure silicon realization that has sufficient margins to function correctly over the product’s entire lifetime. Advanced analog and RF circuit analysis techniques
The advanced architecture of Virtuoso Multi-Mode Simulation uses proprietary techniques—including adaptive time step control, sparse matrix solving, and multicore processing—to provide high performance while maintaining signoff accuracy. It bridges the gap between manufacturability and time to market at advanced process nodes by providing a comprehensive set of statistical analysis tools tailored to IC design. Tight integration with the Virtuoso Analog Design Environment offers user-friendly interactive setup and advanced visualization of statistical results.
Virtuoso Multi-Mode Simulation provides the flexibility to combine design IP from different sources and abstraction levels necessary for the design and verification
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