vlsi ieee 2021


Very large-scale integration is the process of creating an integrated circuit by combining millions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were widely adopted, enabling complex semiconductor and telecommunication technologies to be developed.

VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile,

High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
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Guessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND

ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
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In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm The approximate computing paradigm emerged as a key alternative for trading off accuracy and energy efficiency. Error-tolerant applications, such as multimedia and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still

Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
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There are limitations in CMOS transistor as the technology scales down. The problem of short channel effects (SCE) has become dominant, which causes the malfunction and failure of CMOS circuits. Various devices are proposed to continue extending Moores law and the

Introduction to the Special Issue on the Symposium on VLSI Circuits
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This Special Issue of the IEEE Journal of Solidstate Circuits highlights some of the best papers presented at the Symposium on VLSI Circuits, held on June 15 1 2020. Due to the Covid-19 pandemic, this was the first VLSI Symposium that was held fully virtual. While it is Process variation cause a big variation on chip performance, so we need to apply expensive functional test to do the speed binning. In this work, we propose a machine learning-based chip performance prediction framework. We only consider on-chip ring oscillators frequencySummary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Bio-electronic medicine has become a promising alternative for treating neural diseases. However, the development of bioSummary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. The first carbon nanotube transistors were reported more than 20 years ago. Since then, they have been suggested to hold greatTwo features of shutdown in DCDC converter namely, a smooth shutdown and a fast output voltage discharge are discussed in this paper for Boost and Inverting-Buck-Boost (IBB) for AMOLED display application. The challenges, strategies and circuits for implementing aLarge-size TSV has larger parasitic capacitance, which leads to more resolution challenges. Meanwhile, due to the opposite effect of resistive open fault and leakage fault in the ring oscillator, the coexistence of two types of faults will cause serious test confusion. TheseThe FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture It is generated from Delay Locked Loop (DLL) commonly embedded in almost all VLSI circuit and systemUsing very large scale integrated ( VLSI ) circuit to model power system will keep power system characteristics with less assumptions and higher fidelity. And power system VLSI circuit model has a great potential for high fidelity real time transient simulation2 T. Irisawa et al., Tech. Dig. VLSI symp., pp. 14 K. Sumita et al., Jpn. J. Appl. Phys 4 pp. 98 K. Sumita et al., presented in IEDM W.-K. Kim et al., Tech. Dig. VLSI symp., pp. T12 K.-W. Jo et al., Appl. Phys. LettDecision trees (DTs) are profusely used in machine learning (ML) applications on account of their fast execution and high interpretability. As DT training is time-consuming, in this brief, we proposed a hardware training accelerator to speedup the training process. The proposed

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
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Many researchers inserted two resistors (which increase the size of the circuit and are not recommended in VLSI circuits) and others inserted two diode-connected transistors acting like resistors to solve the problem size in VLSI

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
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To overcome the“von Neumann bottleneck,methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to This article presents highly optimized implementations of the Ed25519 digital signature algorithm [Edwards curve digital signature algorithm (EdDSA)]. This algorithm significantly improves the execution time without sacrificing security, compared to exiting digital signature

Machine-learning-based self-tunable design of approximate computing
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Approximate computing (AC) is an emerging computing paradigm suitable for intrinsic error- tolerant applications to reduce energy consumption and execution time. Different approximate techniques and designs, at both hardware and software levels, have been

Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
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Digital-integrated-circuits students get a baseline design to explore VLSI optimizations requirement. Class size is essentially limited by the cost of AWS credits (for cloud-hosted FPGA-accelerated simulation) and commercial EDA license usage for the VLSI flow

Minimization of Switching Activity of Graphene Based Circuits
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Reduction of power dissipation is a key challenge of VLSI circuits designers. In traditional CMOS-based circuits, dynamic power dissipation occurs due to the switching activity, ie, transitions at logic nodes. In graphene-based circuits, power dissipation is also caused by

Special Session Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
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Integrated circuit (IC) testing presents complex problems that, when the IC becomes large, are exceptionally difficult to solve by traditional computing techniques. To deal with unmanageable time complexity, engineers often rely on human hunches and heuristics

Unsupervised Learning in Test Generation for Digital Integrated Circuits
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VLSI design and test have benefited too: MI has been in use for analog, digital, and memory testing, along with emerging technology-based device test and hardware security . A recent discovery of solving test generation problem using MI opened ample research avenues [11

Performance Analysis of OTFS-based Uplink Massive MIMO with ZF Receivers
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Page 1. Performance Analysis of OTFS-based Uplink Massive MIMO with ZF Receivers Junjuan Feng ∗ Hien Quoc Ngo ∗ Mark F. Flanagan † and Michail Matthaiou ∗ ∗ Institute of Electronics, Communications and Information

Data perturbation and recovery of time series gene expression data
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Weighted node mapping and localisation on a pixel processor array
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pp. 1 2. [15] SJ Carey, A. Lopich, DR Barr, B. Wang, and P. Dudek, A 100,000 fps vision sensor with embedded 535gops/w 256 256 simd processor array, in Symposium on VLSI Circuits. IEEE, 201 pp. C182 C183

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations
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ISPD, pp. 2 2006. Y. Abulafia and A. Kornfeld, Estimation of FMAX and ISB in micro- processors, IEEE T. VLSI Syst, vol. 1 no MD Giles, et al., High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology, in Proc. VLSI Tech.,

Circuit Simulation Techniques of VLSI Circuits
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This paper presents a computer program and simulation technique for fast DC analysis of MOSFET based on VLSI circuits. Time domain analysis of a VLSI based circuit is determined by a piecewise constant waveform approximation. This approximation is determined by

AN OVERVIEW OF DESIGN AND IMPLEMENTATION OF DES ALGORITHM USING FAST 45nm VLSI TECHNOLOGY
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Data is the fuel that drives everyone, it be an individual or a globally established company to do anything. And in the age of digitalization when we are trying to gravitate ourselves from pen and paper to mouse and keyboard, it is essential to make sure that the

A simulation and evaluation scheme for Single Event Effects in VLSI
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Due to the complexity of large scale integrated circuits, it can become time consuming to analyse Single Event Effect (SEE) in large circuits. Hence, this paper proposes a rapid simulation scheme for large scale circuits. It takes advantage of transistor simulation tools

HIGH PERFORMANCE FIR FILTER THROUGH VLSI ARCHITECTURE OF 3 OPERAND PARALLEL PREFIX ADDER
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In the field of VLSI architecture, three operand addition is a popular technique. Carry save adder is commonly used for this purpose. However, in that case, we will encounter the ripple- carry point, which will increase the high propagation delay. For minimising route latency

Review of VLSI Architecture of Cryptography Algorithm for IOT Security
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Privacy is key parameter of communication between or with internet of things. However, some of the challenges arising from the use of this algorithm are computational overhead, use of a fixed S-Box and pattern problems, which occur when handling more complex

VLSI BASED SYNTHESIS OF MOORE FINITE-STATE-MACHINES TARGETING TELECOMMUNICATIONS SYSTEMS
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The optimization methods of the logic circuit of Moore finite-state-machine are proposed. These methods are based on the existence of pseudo equivalent states of Moore finite-state- machine, wide fan-in of PAL macrocells, and free resources of embedded memory blocks

Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design
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This paper presents a newly designed physics-based analytical current transport model of both n-and p-type MoS2 tunnel fieldeffect transistor (TFET) using a high-level hardware language Verilog-Analog (Verilog-A) within Cadence/Spectre. The performance of our

Splay Tree Hybridized Multicriteria ant Colony and Bregman Divergencive Firefly Optimized Vlsi Floorplanning
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Floorplanning is a basic designing step in VLSI circuit to estimate chip area before the optimized placement of digital blocks and their connections. The process of Floorplanning involves identifying the locations, shape, and size of components in a chip. The

Fully Reused VLSI Architectu Encoding for DSRC Applica
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The main aim of this paper is VLSI enactm of adders for high speed utilizing mentor graphics. T Arithmetic Logic Unit (ALU) is the main digital circui all microprocessors. ALU performs arithmetical a logical functions. The objective of this project is intention high

Fault Simulation and Parametric Detection of Faults Using Discre tization in Analogue VLSI Circuits
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In this article we describe new model for determination of fault in circuit and also we provide detailed analysis of tolerance of circuit, which is considered one of the important parameter while designing the circuit. We have done mathematical analysis to provide strong base for

VLSI IMPLEMENTATION OF MODIFIED AES CRYPTOGRAPHY USING SBOX
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With the evolution of The Internet, there has been a huge spurt in online transactions and also an increase in sharing of private, confidential and sensitive information over the web. This in turn has increased the requirement of highly secure and swift methodologies to

DESIGN A LOW-COMPLEXITY VLSI ARCHITECTURE OF AHL MULTIPLIERS FOR FULLY HOMOMORPHIC ENCRYPTION
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Large integer multiplication has been widely used in fully homomorphic encryption (FHE). Implementing feasible large integer multiplication hardware is thus critical for accelerating the FHE evaluation process. Hence in this paper, design low complexity VLSI architecture of

VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Maths
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The wavelet coefficients of certain sub groups convey noteworthy data though the wavelet coefficients of other sub groups dont convey noteworthy data. The sub groups that dont convey huge data need not be encoded. This recoveries critical extra room. Anyway the

Low Power Circuit Design For Footed Quasi Resistance Scheme In 45nm Vlsi Technology-Review
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This paper provides detailed information about earlier research works focused on designing and implementing VLSI circuits in terms of power consumption and leakage reduction through various CMOS based methods. A few existing exploration works were centered on

VLSI Architecture for Radix-4 Booth Complex Multiplier using Cyclic Redundant Adder
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The main objective of this research paper is to design architecture for radix-4 complex Vedic multiplier by rectifying the problems in the existing method and to improve the speed by using the cyclic redundant adder. The multiplier algorithm is normally used for higher bit

VLSI Architecture for Digital IF Filter with Low Complexity using Multi-rate Approach
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Because of restricted recurrence assets, new administrations are being applied to the current frequencies, and specialist co-ops are apportioning a portion of the current frequencies for recently improved versatile interchanges. In light of this recurrence condition

VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
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Reversible computing spans computational models that are both forward and backward deterministic. These models have applications in program inversion and bidirectional computing, and are also interesting as a study of theoretical properties. A reversible

A COST AND POWER EFFICIENT IMAGE COMPRESSOR VLSI DESIGN WITH FUZZY DECISION AND BLOCK PARTITION FOR WIRELESS SENSOR
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This paper presents a novel equipment arranged picture pressure calculation and its exceptionally enormous scope incorporation ( VLSI ) execution for remote sensor organizations. The proposed novel picture pressure calculation comprises of a fluffy choice

AREA AND ENERGY EFFICIENT VLSI ARCHITECTURES FOR LOW DENSITY PARITY CHECK DECODERS BY USING REDUCED DECODING LOGIC
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It has been demonstrated that straight criticism (LFSR) counters are all around adjusted to applications that require wide arrangements of counters and can expand the district and productivity comparative with standard paired counters. Be that as it may, fundamental

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and process data in real