external feedback mode of pll
In the external feedback mode, the external feedback input pin, fbin, is phase-aligned with the clock input pin as shown in . Aligning these clocks allows removal of clock delay and skew between devices. In this mode, one PLL clock output feeds back to the PLL fbin input, becoming part of the feedback loop.
If the internal PLL clock outputs are used in this mode, there will be a phase delay relative to the clock input pin. When using this mode, Altera recommends using the same I/O standard on the input clock, feedback input, and output clocks.