FPGA Implementation of Network Coding Decoder
Network Coding enhances performance of multi-cast network system, e.g., P2P(Peer-to-Peer) system. The Receivers in the network that use network coding technique have to decode the received messages which are encoded by intermediate nodes as well as sender node. Hence, decoding operations of network coding system are more complex than those of normal network system; therefore, performance of decoding operations has a significant influence on performance of the entire network system. In this paper, we address the issues regarding implementation of FPGA-based acceleration engines of Gaussian eliminations on finite Galois field. We compare the decoding performance on FPGAs with SW based implementations on P-4 processor and ARM embedded processor. The result shows that FPGA implementation outperforms contemporary widespread P-4 processor and ARM processors by 20 and 140 times, respectively. Utilizing the technique introduced in this paper, an efficient network coding system could be realized with a low level of computing resources.
There has been rapid improvement in the various types of networks, including traditional wired, wireless, and ADHOC network. There have been modern network technology developments in the area of network, such as hardware devices to perform communication software, communication protocols, etc. Those developments are associated with the diverse spread of data streaming and multimedia applications and services, for example, P2P, VoIP. These applications of the existing server client model, would be more suitable in uni-cast, multicast network than conventional broadcast based communications. For broadcast networks, Edmonds-Karp algorithm is known as a routing scheme to obtain maximum transfer efficiency . However, to find the maximum network transmission efficiency in a multicasting routing scheme is known as NP-hard . Therefore, it is necessary to find a new type of routing scheme for multicast network and network coding is recently proposed as a solution for this. The major difference of network coding from normal routing network is the role of intermediate nodes. When transmitting data, the node in the network coding encodes the data and decodes in the receiving node. However, intermediate nodes in the routing scheme, the received data should be passed without any conversion. Therefore, encoding transferring data is required in intermediate nodes, as well as in a sending node. Thus, for the implementation of network coding techniques require encoding operations in originating node and intermediate node, and decoding operations destination node, respectively. The processing power for this operation has a significant impact on the performance of overall network system, because the encoding and decoding time reflects the whole data transfer time in the system. For example, if the transmission time using network coding is faster by time, let say s, than normal data transfer without network coding, and the overhead to encode/decode the transferred data in the intermediate and destination node is bigger than s, the benefits of network coding become negligible. Sending node and intermediate nodes required in the arithmetic coding operations require small and simple computations, however, the decryption operations performed at the destination node, require a considerable amount of complex operations. Therefore, for efficient decoding operations research is needed. In this paper, network coding techniques for performing fast computation of the decoding method is proposed. Especially the advantages of application specific system such as ASIC (Application Specific Integrated Circuit) or o reconfigurable hardware, FPGA (Field Programmable Gate Arrays), are addressed. Implementation of specialized on-demand system, the results shows that significant improvement in the performance over the general-purpose systems. This paper is organized as follows. Chapter 2 introduces the related research and Section 3 describes each of the network coding and coding and decoding operations are explained in Section 4 describes the FPGA implementation. And the analysis of experimental results in Section 5 and Chapter 6 describes the conclusion.