high-speed FPGA cameras

Differential lossless compression for high-speed FPGA cameras

FREE-DOWNLOAD [PDF] SS Wahl – 2010 –
All these steps are before analog-to-digital conversion (ADC), which is applied to one row after 
The LUPA-3000 CMOS high-speed image sensor provides a pixel rate of 412 MHz per Tclk  on
block RAM can be found in the respective FPGA datasheets on the Xilinx web- page