higher-order voronoi diagrams



Net-aware Critical area extraction for opens in vlsi circuits via higher-order Voronoi diagrams
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Abstract—We address the problem of computing critical area for open faults (opens) in a
circuit layout in the presence of multilayer loops and redundant interconnects. The extraction
of critical area is the main computational bottleneck in predicting the yield loss of a vlsi




IEEE PAPER UNITED STATES