Design and Analysis of High Performance Floating Point Arithmetic Unit




A floating point arithmetic unit designed to perform operations on floating point numbers as well as fixed point numbers. Floating point numbers can support a much wider range of values in comparison to fixed point representation. Floating Point units are mainly used in high speed objects recognition system, high performance computer systems, embedded systems and mobile applications. To represent very small values or very large values, large range is required as the integer representation is no longer appropriate to represent these numbers so these values can be represented by using floating point representation that is based on the IEEE 754 standard. The proposed floating point arithmetic unit is designed using single stage implementation. Due to single stage implementation the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation. So by using single stage implementation the time requires to reach data from input to output becomes less. The proposed unit is designed in VHDL, simulated in Questa Sim simulator and implemented on vertex 7 FPGA.

by Naresh Kumar | Onkar Singh | Harjit Singh “Design and Analysis of High Performance Floating Point Arithmetic Unit”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-1 , December 2020,

URL: https://www.ijtsrd.com/papers/ijtsrd38049.pdf

Paper URL : https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/38049/design-and-analysis-of-high-performance-floating-point-arithmetic-unit/naresh-kumar

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