Optimized Carry Speculative Adder IJTSRD


Arithmetic logic units and digital signal processors widely uses adders. It is the most complicated arithmetic circuits in digital electronics. The existing adders suffer from critical path delay, area overhead and power consumption. Speculative adders are designed with variable latency that combines speculation technique along with correction methodology to attain high performance in terms of low area overhead over the existing adders. In speculative adders the sum and carry generation part is separated to reduce the area overhead. Carry Speculative Adder (CSPA) uses carry predictor circuit to reduce power consumption and to reduce the computational time and it uses error recognition and error correction circuit to find the fault occurred in the partial sum generator and to recover it to get accurate results.

by B. V. Pavan Kumar | M. Lalitha Bhavani | Y. Himanth”Optimized Carry Speculative Adder”

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd11216.pdf

http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/11216/optimized-carry-speculative-adder/b-v-pavan-kumar

call for paper Chemical Engineering, international journal Food Engineering, ugc approved journals for engineering




Optimized Carry Speculative Adder IJTSRD IEEE PAPER





2020 technology trends
2019-TOP-TECHNOLOGIES
2019 papers
2018-TOP-TECHNOLOGIES
2018 papers

IEEE PROJECTS 2019


IEEE PROJECTS CSE 2019
IEEE PROJECTS ECE 2019
IEEE PROJECTS EEE 2019
IEEE PROJECTS VLSI
IEEE PROJECTS EMBEDDED SYSTEM

IEEE PROJECTS


IEEE PROJECTS ECE
IEEE PROJECTS CSE COMPUTER SCIENCE
IEEE PROJECTS ELECTRICAL ENGINEERING
IEEE PROJECTS EEE

IEEE PROJECTS