Low Power digital signal processor
new ULP CMOS process and design methodologies to create circuits
operating at a VDD of 0.5 volts. Since power is proportional to the voltage squared (P = aCV 2 f ),
this reduction in operating voltage results in significant power savings. We developed a synthesiscompatible
Standard Cell Library to enable fast realization of circuits already captured in high-level
languages or prototyped in FPGAs. We selected a Digital Signal Processor (DSP) as a demonstrator
of this technology. DSPs are used in applications that use every clock cycle to run algorithms
against data from sensors and take actions based upon the results. They are often used in portable
devices where battery life and space is limited, but customers still require more functionality, hence
more processing power, and ever smaller packaging. In this paper we describe the steps taken to
develop an example DSP in our technology.
the complete paper
http://www2.cambr.uidaho.edu/tech/sym02_c50.pdf