Low power Pipeline ADC





Which ADC architecture is right for your application
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Most ADC applications today can be classified into four broad market segments:(a) data acquisition,(b) precision industrial measurement,(c) voiceband and audio, and (d) high speed (implying sampling rates greater than about 5 MSPS). A very large percentage of

Vehicle emissions and driving cycles: comparison of the Athens driving cycle ( ADC ) with ECE-15 and European driving cycle (EDC)
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Vehicle emissions constitute the main source of atmospheric pollution in modern cities. The increasing number of passenger cars, especially during the last decade, resulted in composite traffic problems with serious consequences on emissions and fuel consumption

Aperture uncertainty and ADC system performance
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Aperture uncertainty is a key ADC concern when performing IF sampling. The terms aperture jitter and aperture uncertainty are synonymous and are frequently interchanged in the literature. Aperture uncertainty is the sample-to-sample variation in the encoding process. It

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications
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Semiconductor technology is now approaching 100 nanometer feature size and will soon be below 100 nanometer. This technology trend presents new challenges in analog-digital mixed signal circuit design. A mixed signal circuit must be integrated on a single chip along

ADC input noise: the good, the bad, and the ugly. Is no noise good noise
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Input-referred Noise (Code-Transition Noise) Practical ADCs deviate from ideal ADCs in many ways. Inputreferred noise is certainly a departure from the ideal, and its effect on the overall ADC transfer function is shown in Figure 1. As the analog input voltage is increased

Design implementation of low power 3-bit flash adc in 0.18 µm cmos
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This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter ( ADC ). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18 um CMOS Technology. The pre-simulation of ADC is done in T-Spice

8-GSA/S 8-bit ADC system
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We report on an analog to digital converter ( ADC ) system with 8 bit resolution and a sample rate of 8 GSa/s. The system is composed of 2 thick-film hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two

Advanced digital post-processing techniques enhance performance in time-interleaved ADC systems
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Design Challenge of Time Interleaving As mentioned, channel-to-channel matching has a direct impact on the dynamic range performance of a time-interleaved ADC system. Mismatches between the ADC channels result in dynamic range degradation that in an

A 10b column-wise two-step single-slope ADC for high-speed CMOS image sensor
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Slope (SS) ADC , which improves the sampling rate while maintaining the architecture of the conventional SS- ADC for high-speed CIS. To remove the problem of missing code in multi- stage structures, occurring on every boundary between steps of the coarse ADC , the range

Adc architectures iii: Sigma-delta adc basics
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The sigma-delta (Σ- ) ADC is the converter of choice for modern voiceband, audio, and highresolution precision industrial measurement applications. The highly digital architecture is ideally suited for modern fine-line CMOS processes, thereby allowing easy addition of

A CMOS low power, quad channel, 12 bit, 40MS/s pipelined ADC for applications in particle physics calorimetry
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The AD41240 is a 12-bit, four-channel pipelined analog to digital converter fabricated in a rad-tolerant CMOS technology and capable of running at 40 MHz with a power consumption per channel of 150 mW at 2.5 V. The converter core uses a 10 stages pipeline with multiple

An empirical approach to finding energy efficient ADC architectures
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The problem of selecting an optimally efficient ADC architecture at different resolutions is treated using a mainly empirical approach. By analyzing a large amount of measured performance data reported in the literature, the power efficiency of different ADCThere is a need for a universal dynamic model of analog-to-digital converters ( ADCs ) aimed for postcorrection. However, it is complicated to fully describe the properties of an ADC by a single model. An alternative is to split up the ADC model in different components, where

The operation of the SAR- ADC based on charge redistribution
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All Texas Instruments TLV-and TLC-series sequential serial analog-to-digital converters perform successive approximation based on charge redistribution. This article explains the operation of the SAR (successive approximation register)- ADC (analog-to-digital converter)

Understanding high speed ADC testing and evaluation
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SNR, SINAD, worst spur, and IMD are tested using a hardware setup similar to that shown in Figure 1. In production tests, the test hardware is highly integrated, but the hardware principles are the same. The basic setup for dynamic testing includes a signal generator

Progress in the development of a superconductive high-resolution ADC
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This paper is a progress report on the development of a high-resolution analog-to-digital converter ( ADC ) which uses a phase modulation/demodulation architecture. Presented are an analysis of the performance limitations, proposed design improvements, and recent test

A low power column-parallel 12-bit ADC for CMOS imagers
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This paper describes the design of a low-power column-parallel single-slope ADC for CMOS imagers. The design exploits the characteristics of photon shot noise present in imaging signals to reduce power consumption. A prototype imager with a 12-bit column-level ADC

Identification of ADC error model by testing of the chosen code bins
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Abstract− Modelling of ADC allows to utilize testing of selected parameters for determination of its error model over whole operating range. While the integrating ADC model is characterised by polynomial shape of integral nonlinearity, the successive approximation

Statistical performance of Gaussian ADC histogram test
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In this paper, the statistical properties of the Gaussian Histogram Test (GHT) are theoretically evaluated and compared to the corresponding Cram r-Rao Lower Bound (CRLB). In particular, it is shown that the GHT is asymptotically unbiased and efficient. Finally, the GHT

AD systems for processing of low frequency signals based on self calibrate ADC and DAC with weight redundancy
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Abstract. Static and dynamic characteristics of modern AD systems of low signals processing are defined by the parameters of ADC and analog devices. Improvement of accuracy and speed of AD systems is possible due to the usage of self-correcting ADC of bitwise balancingbased CSE PROJECTS

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