Low power Pipeline ADC

Low power Pipeline ADC

A 3.3V, 10bit, 80MS/s pipeline analog to digital converter is implemented in a 0.35um CMOS technology. Emphasis was placed on low power circuit design and system simulation was done to guide the circuit design. A Two-stage comparator and a high performance Op-amp were designed. The achieved ENOB is 9.61 bits. Maximum INL and DNL are 0.2 LSB and 0.3 LSB respectively. The maximum power consumption of whole circuit is 132mW. There are a wide variety of analog-to-digital converter architectures. Each has its strengths and weaknesses that make it suitable for a given set of specifications, such as speed, resolution, power, latency, and area. There are flash, subranging, pipeline, interpolating and folding, successive approximation and others. The comparison between them can be found in . Pipeline ADC has the potential to design low power, high-speed circuit. There are several advantages to this type of architecture. As more bits of resolution are added, the hardware and area grow only linearly since more stages are simply added. Because of inherent digital correction techniques, the accuracy requirements of the sub-ADCs are greatly relaxed allowing low-power comparators. However, because a precision sample-and-hold is required between each stage, fast-settling opamps are required which limit the throughput and increase power consumption. And the number of bits per stage has a large impact on the speed, power, and accuracy requirements of each stage. For fewer number of bits per stage, the subADC comparator requirements are more relaxed, and the inherent speed of each stage is faster. However, more stages are required if there are fewer bits per stage. Furthermore, the noise and gain errors of the later stages contribute more to the overall converter inaccuracy because of the low interstage gain. Thus, high-speed, low-resolution specifications favor a low number of bits per stage, where low-speed, high-resolution specifications tend to favor higher number of bits per stage. PIPELINE ADC ARCHITECTURE The ADC uses pipeline 1.5b/stage architecture with 9 stages as shown in Fig 1. Each stage generates 2 bits with a sub-ADC, subtract this value its input, and amplifies the resulting residue by a gain of 2. The sample and hold function is realized by the buffering switch-capacitor gain blocks allowing concurrent processing. The resulting 18 bits are delayed accordingly and combined with digital correction to yield a 10-bit at the output of ADC.

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