low power receiver for wcdma
COMPUTER COURSE ONLINE
The desire for ubiquitous information access continues to drive the development of applications and services for new wireless systems. The success of these systems will depend heavily on the ability to provide high capacity while maintaining low cost, small form factor and low power consumption in the portable devices. These characteristics may be achieved by adhering to three design strategies. First, at the system level, implementation issues must be considered even during the earliest stages of system definition. Selecting system features which allow for relaxed hardware requirements is paramount to achieving single-chip low-power receiver implementations. Second, efficient implementations require careful partitioning of receiver functions between analog and digital hardware. The rapid improvements in mainstream CMOS technology facilitate the integration of increasingly more functionality onto a single chip. In particular, advanced signal processing algorithms, which are very amenable to low-power digital design techniques, can be used to relax the analog hardware requirements without sacrificing overall system performance. Third, low-power implementation techniques are required to minimize the power consumption of the analog front-end. Despite efforts to simplify the analog hardware, the analog front-end can still dominate overall receiver power consumption.