Low Power SRAM using Active DRG BL Charge Recycling-free research papers, vlsi


A Novel Scheme for Low-Power SRAM using Active-DRG BL Charge
Recycling for Read/Write Operations and Leakage Reduction for
Embedded-Multimedia Memory Applications

The Low-Power and HighPerformance CMOS devices is an industry buzzword these days. Among the various embedded memory technologies, SRAM is able to provide the highest performance while maintaining low standby power consumption. High leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Therefore, identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for battery operated portable low-power applications. This paper targets the power reduction in a conventional SRAM at the circuit level by reducing the leakage power consumption. To the best of my knowledge, this paper proposes a novel approach for over-all power reduction in an SRAM by introducing the Active-DRG configuration with the Bit-Line CR technique (W/R) for the first time. It is proposed that while the memory is in the active mode, the power optimization is achieved through BL-CR and when the memory is not in use, i.e., in the standby mode, the leakage power is achieved through DRG scheme. The technique is given the name as, Active-DRG Scheme. In this new memory architecture the power reduction is achieved for both the dynamic and the standby mode.

Advancement of semiconductor technology has driven the rapid growth of very large Scale Integrated (VLSI) systems for increasingly broad applications, including highend and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have also become increasingly more complex, ranging from static to dynamic and volatile to nonvolatile. Among embedded memories, six-transistor (6T)-based static random access memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due to its superior speed and full compatibility with logic process technology. But as the technology scaling continues, SRAM design is facing severe challenge in maintaining sufficient cell stability margin under relentless area scaling. Meanwhile, rapid expansion in mobile application, including new emerging application in sensor and medical devices, requires far more aggressive voltage scaling to meet very stringent power constraint. Many innovative circuit topologies and techniques have been extensively explored in recent years to address these challenges . The active power of the SRAM is mainly consumed in bit lines and data lines, because the SRAM charges and discharges the high capacitive bit lines and data lines in read and write cycles. As the bit width of SRAM becomes larger for high-performance applications, the power consumption in bit lines and data lines continues to increase. In the conventional SRAM, the read power is smaller than the write power. In read cycles, the swing voltage of bit lines is limited to a small voltage. But, in write cycles, a full swing voltage is used. Several techniques have been proposed by the researchers in the domain to reduce the write power by lowering the write swing voltages of bit lines . In [6] a technique is proposed which significantly reduces the write power by using bit-line charge-recycling [6]. This bit-line charge-recycling reduces the swing voltages to a low swing voltage (∆VBL). It is a very powerful method to reduce the write power in bit lines, because the power savings ratio of the chargerecycling is ∆VBL/VDD, whereas that of the low swing is ∆VBL/VDD. However,this technique has

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