low power vlsi IEEE PAPER 2017

Design Methodologies and Strategies for Low Power VLSI
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Low power has emerged as a principal theme in todays world of industries. Power dissipation has become an awfully necessary thought as performance and area for VLSI Chip vogue. With shrinking technology reducing power consumption and over all power

A Configurable and Low Power Hard-Decision Viterbi Decoder in VLSI Architecture
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Abstract-Convolutional encoding and viterbi algorithm are basic concepts of error correction method. Viterbi algorithm is one of decoding method for data error correction. In VLSI area, the design challenges are usually about its power, area consumption, speed, complexity,

Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design
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Abstract:-As the in semiconductor industries progress by following Moores law faithfully from last five decades, and integrating more transistors along with functional circuits on a single chip periodically with every coming process technology. However, this progress help in

Low Power Consumption Using CMOS VLSI Design in Modern Trends
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The revolution of wireless communication, portable and mobile devices has consistently demanding the designer to design the device for low power consumption. Power loss becomes a main parameter of integrated circuits, particularly for portable computers and

Design and Analysis of Various Standard Multipliers Using Low Power Very Large Scale Integration (VLSI)
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Abstract-This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard multipliers using Verilog HDL. Multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and Gain-Cell eDRAM (GC-eDRAM) is an interesting, high-density alternative to SRAM and conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications, including ultra-low power systems such as biomedical implants [17], wireless CSE PROJECTS