Noise Modeling for RF CMOS Circuit Simulation

The RF noise in 0.18- m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for shortchannel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1 noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs. T HE EVER-CONTINUING downscaling of CMOS technologies has resulted in a strong improvement in the RF performance of MOS devices . Consequently, CMOS has become a viable option for analog RF applications and RF systems-on-chip. For the application of modern CMOS technologies in low-noise RF circuits, accurate modeling of noise is a prerequisite

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