Power-delay optimization


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Power-delay optimization in VLSI microprocessors by wire spacing

FREE-DOWNLOAD [PDF] K Moiseev, A Kolodny… – ACM Transactions on Design …, 2009
Intel Corporation The problem of optimal space allocation among interconnect wires
in a VLSI layout, in order to minimize the switching power consumption and the
average signal delay, is addressed in this article. We define 




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