Power Gating-Circuits, Design Methodologies, and Best Practice for Standard Cell VLSI Designs

Power gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

CMOS is the technology of choice in contemporary VLSI designs. The mechanism by which a CMOS circuit consumes power is well understood in terms of both its dynamic and static components. The static component, which is unrelated to the useful operation of the circuit, is a result of device leakage currents caused by various physical phenomena [Roy et al. 2003]. Leakage currents flow all the time: active leakage occurs when a circuit is switching and standby leakage when it is idle. Periodic quantitative analyses appearing in the literature suggest that active leakage is an increasing proportion of total power consumption, reaching 30% for 65-nm technology [Mair et al. 2007; Rusu et al. 2007]; active leakage is therefore important in stationary systems where active mode dominates the total operation time. Standby leakage is, in general, smaller than active leakage (e.g. about 10% for a 100 MHz device operating at room temperature [Ye et al. 1998]). Device stacking significantly reduces leakage when several MOS devices in series are turned off, but this requires a lot of time, typically much longer than a clock period. The difference between active and standby leakage increases with clock frequency [Ye et al. 1998]. Nevertheless, standby leakage does increase with frequency, and also becomes a higher proportion of total standby power consumption. This makes standby leakage an important concern in the design of mobile systems, which tend to operate in standby, or sleep, mode for most of the time. There are three main components of leakage, namely subthreshold, gate tunneling, and junction tunneling leakage [Roy et al. 2003]. The relative importance of these components differs with the technology, the temperature, the style of circuit, and so on. For instance, gate leakage is important in SRAM circuits since they typically rely on devices of larger gate length to reduce random dopant variations, while subthreshold leakage is dominant in logic circuits [Narendra and Chandrakasan 2005]. Many circuit design techniques have been proposed to reduce leakage, in particular subthreshold leakage, both in active and sleep modes, and we will review them in Section 2. Power gating is the circuit design technique that has been most widely used in industrial products. It is employed in standard-cell library designs, supported by commercial CAD tools and foundry design services [TSMC], and has been adopted as the industry standard [Keating et al. 2007]. Power gating is conceptually very simple: a circuit is cut off from its power supply in sleep mode by means of a current switch. However, the design of a power-gated circuit especially for standard-cell VLSI, involves many careful considerations, which we will review in Section 3. These include retaining data by isolating outputs and the use of retention flip-flops, the design and sizing of current

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