power scaleable and low power pipeline ADC using power resettable opamps

A 10 bit pipeline Analog-to-Digital Converter (ADC) is designed such that its average power is scaleable with sampling rate over a large variation of sampling rates. Fabricated in CMOS 0.18μm technology, while having an area of 1.21mm 2 , the ADC uses a novel fast Power Resettable Opamp (PROamp), to achieve power scalability between sampling rates as high as 50Msps (35mW), and as low as 1ksps (15μW), while having 54-56dB of SNDR (at Nyquist) for all sampling rates. A current modulation technique is used to avoid weakly inverted transistors for low bias currents, thus avoiding less accurate simulation, poorer matching, and increased bias sensitivity. The PROamp due to its short power on/off time also affords reduced power consumption in high speed pipeline ADCs, where opamps can be completely powered off when not required. Measured results show an ADC using PROamps has 20- 30% less power than an ADC which does not use PROamps.

at have a power which reduces with sampling rate can significantly reduce manufacturer and customer costs. A single power scaleable ADC can be used by a manufacturer to target multiple applications with different performance requirements saving development costs, and reducing time to market. Similarly a customer can purchase only a single ADC model to meet requirements for multiple applications. Low power applications requiring multiple operating speeds and multiple standard compliancy (e.g.: mobile, biomedical, etc.) also benefit from a single ADC with scaleable power Conventional CMOS digital logic consumes mainly dynamic power during output transitions, thus power management in the digital domain can be easily achieved. In other words, if a CMOS digital block is clocked slower, less power is consumed as fewer output transitions occur. Thus digital sub-systems automatically adjust their power according to their operating speed. As ADCs are dominated by analog circuitry, ADCs do not have a power that optimally scales with operating speed. Analog power is dominated by static power, where fixed bias currents and fixed supply voltages are used for specific operation speeds (where P=IV).Thus analog power is scaled with operating speed if the bias current and/or supply voltage to the ADC are made functions of the operating speed. As extended voltage scaling degrades Signal to Noise Ratios (SNR), power is often scaled in ADCs by only scaling bias currents with operating speed (i.e. sampling rate, fs). Since analog subsystems are carefully characterized and optimized by setting specific bias currents, a significant variation of bias currents to reduce power with speed, leads to lengthy design times, and costly post design verification to validate functionality over the multiple design corners. Furthermore, as bias currents are reduced, transistors shift from strong to weakinversion operation. Current mirrors in weak inversion match substantially poorer, resulting in sub-optimal power distribution, and are susceptible to significant performance degradation due to a high sensitivity of drain-source currents to bias voltages. As such designs in weak inversion have a poorer yield unless a conservative design approach is taken. In this dissertation a 10-bit pipeline ADC is presented which uses pulse-width modulated currents to achieve power scaleability over ultra wide variations in sampling rate, without relying on excessive current scaling, thus avoids placing the ADC transistors deep in weak inversion for very low sampling rates. By sequencing the operation of each pipeline stage according to timing set by a digital controller that completely powers off the pipeline ADC between conversions, a power scaleable range which multiplies the power scaleable range of current scaling by over 1000x is shown to be achieved in a functional 0.18μm CMOS prototype. Although powering off the ADC between conversions is a technique used in industry to achieve scaleable power, such ADCs have been restricted to slower architectures (<500ksps). This work represents the first known ADC which using a pipeline architecture is capable of achieving power scaleability at sampling rates as high as 50Msps, and as low as less than 1ksps (i.e. power scaleable range of >50,000), without resorting to extensive current scaling (thus avoiding the problems of transistors biased deep in weak inversion). To implement the power-scaleable architecture, a novel Power Resettable Opamp (PROamp) was developed which is capable of completely powering on/off in a very short time interval. The short on/off time of the novel opamp also allows for an improved ADC figure of merit, as opamps can be completely powered off when not required (e.g.) the sampling phase of a sample and hold or pipeline Multiplying Digital to Analog Converter (MDAC). As such, the pipeline ADC was designed such that the opamp is only powered on during hold phases in sample-and-hold and MDAC circuits. To quantify the reduction in power the ADC was designed with an additional mode of operation where when the pipeline ADC operates at full rate, the opamps always remain on (i.e. the ADC operates as a conventional pipeline ADC). Measured results show power is reduced from 44mW to 35mW when only powering the opamps during the hold phase, for fs=50Msps, while achieving an accuracy of ~55dB SNDR (~1.6pJ/step). As such the PROamp is shown to be a highly useful block to enable advanced power management in high-speed analog circuits. The dissertation details the development of an ADC that has power scaleability over very wide range of sampling rate. Chapter two provides the reader with background information as to why ADCs are required in signal processing and how pipeline ADCs operate at the system level. Chapter three outlines common circuit implementations of key sub-blocks in the pipeline ADC, as well as addressing essential design trade-offs at the circuit level. Chapter four addresses the dependency of power with sampling rate, where issues associated with current scaling are elaborated. In chapter five the circuit implementation for this dissertation, including the digitally controlled pipeline architecture, and 50Msps Pipeline ADC with reduced power using the Power Resettable Opamp is described. Key simulation results and performance limitations are discussed and analyzed.

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