project in xilinx fpga

FPGA based Implementation of Efficient Arch. for a Biquad Filter
Xilinx 10.1 ISE, FPGA Spartan-3AN

The project deals with the implementation of area efficient Biquad filter using folding technique and register minimization techniques. Folding minimizes the no. of components required but increases the registers, hence we minimize number of registers using register minimization technique called lifetime analysis. Hence comparing the 3 architectures shows the minimization of the resources and further the architecture is implemented FPGA Spartan 3A kit.