rfic verification requirements




Verifying high-performance RFICs is challenging because the circuit simulator needs to predict circuit linearity and noise with a very high degree of accuracy, with silicon as the reference. Simulation accuracy, which translates into circuit dynamic range noise margin, is critical to our ability to meet specifications without costly respins.

Our baseline verification flow for analog and RF circuits relies on traditional SPICE simulations with tight tolerances to deliver the required accuracy. By traditional SPICE, we mean a tool that uses standard foundry transistor-level device models without approximations, finds and maintains a true DC operating point, solves the full matrix at every timestep, and maintains SPICE-level relative tolerance (reltol).

Our baseline flow works well for small circuits, but it breaks down with the complex circuits that our RFICs require. Traditional SPICE simulators cannot keep up, either in terms of performance or capacity. We have the additional requirement of functional verification of transceivers at the full-circuit level with as much accuracy as possible to detect circuit errors prior to tapeout.




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