scan clock control for test time reduction
Dynamic scan clock control for test time reduction maintaining peak power limit
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P Shanmugasundaram… – VLSI Test Symposium ( …, 2011 –
Abstract We dynamically monitor per cycle scan activity to speed up the scan clock for low
activity cycles without exceeding the specified peak power budget. The activity monitor is
implemented either as on-chip hardware or through pre-simulated and stored test data. In