Selectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance
Structured ASIC, which consists of a homogeneous array of tiles, suffers from large delay and area due to its inherent regularity. A new lithography method called selectively patterned masks (SPM) is proposed. It exploits special masks called masking masks and double exposure technique to allow more than one types of tiles to be patterned on the same wafer. The result is a heterogeneous array of tiles, which relaxes regularity in structured ASIC. A new structured ASIC based on SPM is proposed; tile and routing architectures, design ﬂow, and tile packing and routing algorithm are all addressed. Experiments in 45-nm technology show that, compared to ASIC, the proposed structured ASIC exhibits 2.0 times of area when circuits are optimized for area and 1.2 times of delay when they are optimized for delay. Both ﬁgures represent substantial improvement over conventional structured ASIC.
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