slits in layout




For wider metal lines
the metal expands repeatedly with enough force, the metal will eventually
crack the isolation and passivation layer that protect the wafer. Impurities and
particles will work their way onto the chip, react with the different materials, and
cause the chip to fail or work unreliably.

To address this problem, layout designers are required to put slits or holes
in the metal at regular intervals. This technique has the effect of reducing a very
wide metal to one that has many smaller areas that happen to be connected
together.




IEEE PAPER UNITED STATES