USB 3.0 – A Cost Effective High Bandwidth Solution for FPGA Host Interface
The USB 3.0 has revolutionized the world of desktops and mobile devices by bringing much higher bandwidth and better power delivery compared to its predecessor USB 2.0. USB 3.0 (later renamed as USB 3.1 Gen 1) offers data rate of 5Gb/s or a whopping theoretical bandwidth of 625MB/s[1]. This is more than 10 times the theoretical maximum bandwidth of USB 2.0.[2] While practically available bandwidth for end user applications can be lower depending on the hardware and firmware solutions chosen(will discuss this later in this document), USB 3.0 offers a great value proposition that cannot be ignored. Other host interface solutions available in the market such as PCI Express, Thunderbolt and Ethernet can outperform USB 3.0 in many scenarios, but all these interfaces are relatively more expensive to implement especially in low volume segments. Also, USB 3.0 offers better power delivery compared to the other available solutions. This can further reduce the total cost of the solution/end product.
A USB Primer Universal Serial Bus also known popularly as USB is a standard developed by USB Implementers Forum (USB-IF). Released in 1996, the standard specifies Cables, Connectors, Protocols and Power Delivery between Personal Computers/Mobile Devices and Peripheral Devices. USB was designed from the ground up to eventually replace legacy peripheral connectivity solutions such as Serial Ports and Printer Ports. This is achieved by defining several Device Classes such as Human Interface Device Class (HID), Printer class etc. USB defines four types of transfers – Control, Isochronous, Bulk and Interrupt. Each transfer type offers varying bandwidth and different delivery guarantees, usually trading one with the other. Transfers happen between logical data source/sink pairs established in host and peripheral known as Endpoints.

Endpoint offers easy segregation of traffic and allows multiple agents on the Host and Device communicate transparently despite the fact that USB has only one pair of RX/TX physical channels to share. A logical connection between a pair of corresponding Endpoints on Host and Device is known as a Pipe. Host agents such as applications and drivers can open a Pipe to the peripheral device and do reads and write to move data. Endpoints are grouped in to Interfaces that represent part of a device function. For example, USB CDC class devices use control Endpoints for enumeration and device management, Interrupt Endpoints for event notifications and Bulk Endpoints for data transfer. Certain devices support more than one function and are called composite devices.

USB 3.0 is the third revision of USB specification rolled out by USB Implementers Forum which supersedes USB 2.0. USB 3.0 offers lots of improvements in bandwidth, power management and delivery, efficient bus usage etc. USB 3.0 connector defines a pair of USB2.0 compatible signals (D+/D-) to ensure that USB 3.0 hosts are compatible with USB2.0 legacy devices. The SuperSpeed transmitter and receiver differential pairs provides the 5.0Gbps channel for USB3.0 “SuperSpeed” data transfers. As one can see later in the document, availability of a USB 2.0 interface on the same connector is very useful for designs containing FPGA device as it provides a sideband mechanism to provide other services such as FPGA configuration, Board health monitoring services, Power supply configuration etc without sacrificing bandwidth on the USB3.0 channel. USB 2.0 can also be used as a fallback channel when the upstream host or hub that does not support USB3.0. Examples of utilizing the USB2.0 channel for other purposes is explained elsewhere in this document. USB 3.0 was renamed to USB 3.1 Gen 1 in July 2013. USB 3.1 Gen 2 specification defines a “SuperSpeed+” transfer mode at a rate of 10Gbps. USB 3.2 is in the horizon that offers up to 20Gbps over two lanes on a USB Type C connector.

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