VHDL design and simulation of a fast beam loss interlock for TTF2

vlsi

VHDL design and simulation of a fast beam loss interlock for TTF2-download

Abstract The TTF2 fast beam loss interlock provides different modes of protection. Based on the
differential beam charge monitoring over a macropulse, a pulse slice or bunch-by-bunch, the
signal processing time should be as short as the bunch repetition period (110 ns). The



IEEE PROJECTS
COMMENT vlsi



 



FREE IEEE PAPER