VLSI Implementation of a Low Complexity LLL Lattice Reduction Algorithm for MIMO Detection
Lattice-reduction (LR)-aided successive interference cancellation (SIC) is able to achieve close-to optimum error-rate performance for data detection in multiple-input multiple-output (MIMO) wireless communication systems. In this work, we propose a hardware-efﬁcient VLSI architecture of the LenstraLenstra-Lovász (LLL) LR algorithm for SIC-based data detection. For this purpose, we introduce various algorithmic modiﬁcations that enable an efﬁcient hardware implementation. Comparisons with existing FPGA implementations show that our design outperforms state-of-the-art LR implementations in terms of hardware-efﬁciency and throughput. We ﬁnally provide reference ASIC implementation results for 130 nm CMOS technology.
Multiple-input multiple-output (MIMO) technology enables high spectral efﬁciency by using multiple antennas at both sides of the wireless link and by transmitting multiple data streams concurrently in the same frequency band. The task of the MIMO detector is to separate the spatially multiplexed data streams at the receiver. Maximum likelihood (ML) detection provides optimum error-rate performance, but the associated computational complexity is high, in general, and hardware efﬁcient VLSI implementation of ML detection is challenging . To reduce the complexity associated with MIMO detection, linear detection or successive interference cancellation (SIC) can be employed. The complexity reduction associated with such low-complexity detection schemes comes, however, at the cost of a signiﬁcantly degraded error-rate performance. Lattice reduction (LR) techniques were proposed to reduce the performance gap between low-complexity MIMO detection schemes and ML detection . The basic idea is to perform sub-optimum detection based on latticereduced channel matrices. This approach shifts most of the computational complexity to the preprocessing stage, which needs to be performed only when the channel state changes. Unfortunately, most communication standards require this preprocessing step to be performed under tight latency constraints, which requires high-speed LR implementations. So far, hardware-implementation aspects of LR have only been addressed in for MIMO detection and in for MIMO precoding.
we introduce a low-complexity LR algorithm for SIC-based MIMO detection that is based on the Lenstra-Lenstra-Lovász (LLL) algorithm and employs the Siegel criterion and . In an attempt to reduce the computational complexity, we relax the size reduction condition . We further employ early termination (ET) of the algorithm based on the actual execution time, in order to guarantee a minimum throughput. To reduce the performance loss in the presence of ET, we reverse the processing order of the elements in the LR algorithm. Finally, we describe a corresponding hardware-efﬁcient VLSI architecture which, compared to state-of-the-art FPGA implementations , achieves at least a ﬁvefold throughput increase with only a slightly higher hardware complexity. We also provide reference implementation results in 130 nm CMOS technology