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Effect of Line Parasitic Variations on Propagation Delay in Global VLSI Interconnects}
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KG Verma, R Singh, BK Kaushik… – IJCA Special Issue on … –
ABSTRACT Process variation is considered to be a major concern in the design of circuits
including interconnect pipelines in current deep submicron regime. Process variation results
in uncertainties of circuit performances such as propagation delay. The performance of



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