vlsi interview questions and answers
Why must transistors be provided with bulk connections?
What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why?
To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules?
What is their major purpose?
How are design rules created?
17) What are width rules, space rules, and overlap rules?
18) What is avertical connection diagram
What is it used for?
vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes. 19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why?
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Hi, Thanks , I am looking for video on vlsi interview, any body any help will be appreciated Ravi
Hi everybody, As an expert in this domain, I would like to write my comments 1. Go through VLSI book from beginning to the end 2. If possible solve all the problems at the end of the chapter 3. Most basic question is draw digital gates using transistors, difference between bipolar and cmos , analog and digital 4. Go through the details on your project5. Refresh your circuit theory, basic LCR circuit , transfer function , .. and best of the luck Guru
See the list of vlsi interview questions at
1. Are you familiar with the term MESI?
2. Are you familiar with the term snooping?
3. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
4. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
5. You have a driver that drives a long signalconnects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
6. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
7. Explain the operation considering a two processor computer system with a cache for each processor.
8. What are the main issues associated with multiprocessor caches and how might you solve it?
9. Explain the difference between write through and write back cache.
10. What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++?
11. Have you studied busses? What types?
12. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
13. How many bit combinations are there in a byte? 14. What is the difference between = and == in C?
When will you use a latch and a flipflop in a sequential design?• Design a 1-bit fulladder using a decoder and 2orgates?• You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why?• In a SRAM circuit, how do you design the precharge and how do you size it?• In a PLL, what elements(like XOR gates or Flipflops) can be used to design the phase detector?
1. Give two ways of converting a two input NAND gate to an inverter
2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
3. What are set up timehold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level implementation of the same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence ofarriving serially from a signal line?
14. Design any FSM in VHDL or Verilog.
15. Explain RC circuit’s charging and discharging.
16. Explain the working of a binary counter.
17. Describe how you would reverse a singly linked list.
discussion on asic interview question
there is no or small difference between asic interview and vlsi interview, some vlsi interview questions I am posting, which
1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signals, while NMOS networks are used to product low (0) signals? PMOS is used to drive ‘high’ because of the threshold voltage-effectThe same is true for NMOS to drive ‘low’.A NMOS device cant drive a full ‘1[ch8242] and PMOS cant drive full ‘0[ch8242] Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing
2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean? The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)If given only one number it’s the width combined with a default length
3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four? To limit the height of the stack. As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be.
4) What is meant by static and dynamic power with respect to the operation of a CMOS gate?
5.Why do CMOS gates dissipate close to zero static power?
6.Why is the static power not exactly zero?
7. What is a transmission gate, and what is it used for typically?
8. Why are transmission gates made with both PMOS and NMOS transistors?
9) What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal’s path?
10) What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal?
11) What is the difference between a mask layer and a drawn layer in an IC layout? Why do layout designers usually only specify drawn layers?
12) In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each? A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it’s off grid with 45 degree angle. Polygon is always on-grid, unless it’s a copy and flip. However, polygon is hard to edit and work with.
13) What is the difference between a contact and a via? What is astackedvia process? Via: a contact between two conductive layers. Contact:Opening in an insulating film to allow contact to an underlying electronic device. The placement of vias directly over the contacts or other,lower vias is known as stacked via.
14) Why is it that NMOS transistors can be created directly in a P-type substrate, whereas PMOS transistors must be created in an N-type well?
15) Why must transistors be provided withbulkconnections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why? To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit
16) What are process design rules? What is their major purpose? How are design rules created?
17) What are width rules, space rules, and overlap rules?
18) What is avertical connection diagram ? What is it used for? vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes.
19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why?
20) What are the major advantages of hierarchical IC design? Concurrent design • Design reuse • Predictable schedules
IMPORTANT FOR ALL VLSI CANDIDATE
1. before going for these types of interview questions , study any good vlsi book
2. measure your capability by your shelf, you can go to any chapter end questions and see how many questions you can solve
3. for experienced professionals prepare one of your projects thoroughly, most common question for vlsi experienced professionals is explain one of the projects , remember you have to explain relevant experience which are suitable for the job requirement
4. for fundamentals you may be asked on deep sub micron technology , channel length modulation, mos characteristics, noise ,
vlsi interview questions and lots of vlsi articles
The NOR and NOT gates in the figure below have a propagation delay of tpd = 0.5 ns. What is the propagation delay of the longest path through the circuit?
8 What is a tri-state bus and what is it used for?
a. A tri-state bus has 3 possible states: 0,1,Z and is used for bi-directional bus
b. A tri-state bus has 3 signals only and is used for write control
c. A tri-state bus has 3 possible states: 0,1,X and can indicate when the bus is in unknown state
d. None of the answers is true
QuestionHow many transistors are required in CMOS to implement a NAND gate?
a. 2
b. 4
c. 8
d. NAND gate can not be implemented in CMOS, but only in NMOS
QuestionWhich of the following represents XOR?
a. Z = (X and not Y) or (not X and Y)
b. Z = (X and Y) or (not X and not Y)
c. Z = not (not X and not Y)
d. Z = (X and not Y) and (not X and Y)
verilog interview questions answers CSE PROJECTS