VLSI Layout-Algorithms for floorplanning




are classified in two classes of approaches, iterative approaches and constructive approaches. Iterative approaches produce floorplan with better areas utilization but they are slower then constructive algorithms. An iterative approach starts with one initial solution, evaluate it and then generate more such solutions from available solution. At each stage, an iterative approach evaluates new solution and compares it with earlier available results and keeps only promising solutions. In these approaches, an algorithm run up to either reaching timeout or based on some criteria such as no more improvement in results. While in case of a constructive approach a feasible solution is generated gradually from available inputs using some techniques and principles. We propose and investigate two constructive algorithms based on the notion that grouping blocks having nearly same area in a floorplan produce better results than placing blocks having wide difference in area. In both algorithms, exhaustive search procedure is carried out at each step to place four or less blocks at a time to get a floorplan having best area utilization. This exhaustive search procedure is repeated in bottom up to construct a floorplan. . Objectives of floorplanning problem is either area optimisation; wire length optimisation or both. Although wire length optimisation is also critical to VLSI physical design but we will focus on only area optimisation.






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