# VLSI Layout-Algorithms for floorplanning

are classified in two classes of approaches, iterative approaches and constructive approaches. Iterative approaches produce floorplan with better areas utilization but they are slower then constructive algorithms. An iterative approach starts with one initial solution, evaluate it and then generate more such solutions from available solution. At each stage, an iterative approach evaluates new solution and compares it with earlier available results and keeps only promising solutions. In these approaches, an algorithm run up to either reaching timeout or based on some criteria such as no more improvement in results. While in case of a constructive approach a feasible solution is generated gradually from available inputs using some techniques and principles. We propose and investigate two constructive algorithms based on the notion that grouping blocks having nearly same area in a floorplan produce better results than placing blocks having wide difference in area. In both algorithms, exhaustive search procedure is carried out at each step to place four or less blocks at a time to get a floorplan having best area utilization. This exhaustive search procedure is repeated in bottom up to construct a floorplan. . Objectives of floorplanning problem is either area optimisation; wire length optimisation or both. Although wire length optimisation is also critical to VLSI physical design but we will focus on only area optimisation.

Comparisons between slicing and non-slicing approach of vlsi layout floor planning

Slicing representation has some advantages such as smaller encoding cost and solution space bringing faster runtime for packing. Furthermore it is flexible to deal with hard, preplaced, soft and rectilinear blocks. However in real designs optimal solution might not be in the solution space of slicing structure. While with non-slicing representation optimal solution might be achieved but it needs more evaluating runtime for packing then slicing approach.

Constraints in Floor planning of vlsi layout

In floorplanning, it is important to allow users to specify placement constraints. Three common types of placement constraints are preplaced constraint, boundary constraint, and range constraint. For preplaced constraint, we require a block to be placed exactly at a certain position in the final packing. For boundary constraint, we require a block to be placed along one particular side of the final floorplan: on the left, on the right, at the bottom, or at the top. This is useful when users want to place some specific block along the boundary for inputâ€“output connections. For range constraint, we require a module to be placed within a given rectangular region in the final packing. This is indeed a more general formulation of the placement constraint problem and any preplaced constraint can be written as a range constraint by specifying the rectangular region such that it has the same size as the module itself. Some representations and algorithms for floorplan are extended for above given constraints.