VLSI Technology, Wafers and Impact on Nanotechnology





This paper presents a detailed study of the present VLSI technological aspects, importance and their replacement or combination with the Nanotechnology in the VLSI world of silicon semiconductors. Here authorsbringout the nanotechnologyinSiliconworldwhich invariably means shrinking geometry of CMOS devices to nano scale. This also refers to a new world of nanotechnology where chemists are working in manufacturing of carbon nanotubes , nano devices of varius materials of nano dimensions without even knowing howthiscould changethewholeworldofSiandCMOS technology and the world we live in.

The VLSI technology means 10s of millions of CMOS transistorsinmicronsona siliconwaferofafewcm dimensions. GaAsdevicesalsoarefoundinafew applications butSi dominates the VLSI chips. The Moores law continues to hold good with the continuous advances in the VLSItechnology anddesignissues.Alsodifferent materials are replacing the conventional silicon wafers and aluminum metal interconnects to achieve more density per chip to cope up with the miniaturization in the technology and it is believed that their might be a dead end to the CMOS technology in future if we try to keep on going with this trend . Silicon wafers have been replaced with the Silicon-on-Insulatorand low k-dielectriccostofchipmasksand next-generationfabricationplantstotally replacingtoday‟s foundries and copper interconnects leading to the production of CMOS process with effective line widths of less than 120 nm. In spite of advances this industry and research, a threat to economic issues holds as the continuing scaling of Silicon transistorsbringsaboutanew,exciting era ofnano-scale technology to silicon foundries.

II. Nanotechnology and CAEN Chemically assembled electronic Nanotechnology (CAEN), a form of electronic nanotechnology (EN), that usesSelf-alignmentto constructelectroniccircuitsoutof Nanometerscaledevices.CAENdevicesareapromising alternative to CMOS-based devices; particularlyCMOS based reconfigurable devices . FollowingInternational Technology Roadmaps for Semiconductor (ITRS), advanced siliconfoundriesare manufacturingafullspectrumof integratedcircuit products down to 90-nm technology node today. A few companies like IBM and INTEL have launched afewchipsusing65nm technologies,eg.Quadcore processor using 65nm . At this stage, many of the device characteristics are no longer a straightforward extension of past generations. Scaling is beyond simple shrinking of 3D physical dimensions of devices; it involves the changing, or „straining‟, oftheatomicspacingtoaltertheSilicon electronic properties for better performance.

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