what is timing closure
FREE IEEE PAPERS
Timing closure is often the most difficult task in designing
a chip owing to the fact that a logic gate’s timing behavior (or
speed) varies greatly at different temperatures, supply voltages, and
process conditions under which the device is built and operated.
Moreover, a logic gate’s speed is also affected by the drive and load
environment surrounding the logic gate. Timing closure means that
the chip must run at a designed speed (represented by clock frequency)
reliably under all conditions. This is not an easy task to achieve,
especially when the process shrinks to even finer geometries and wire
delays become more dominating in the overall delay equation.