Design of Low Noise Low Power Linear CMOS Image Sensors


The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important for producing imaging systems that can b e manufactured with low cost, low p ower, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampliers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can b e reduced using the closed loop opamp buers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and oset mismatches in the sample and hold ampliers all of which are not compensated by CDS. Sample and hold amplier oset mismatch is identied as the largest contributor to FPN. The digital interface issues of CMOS imagers are also studied. The design of a 12-bit pipelined analog-to-digital-converter (ADC) in standard CMOS technology is presented. The integration of this ADC onto the imager chip would result in a digital image sensor.

Over the past decade, developments in image-sensor technology brought new image capture equipment to the market. Camcorders and Digital Cameras are the well known products of this development. At the same time due to improvements in wireless and portable electronics, there is increasing demand for miniaturized, low-power and cost ecient imaging systems. This trend has led to a shift in technology from Charge Coupled Device (CCD) based image sensors to Complementary Metal Oxide Semiconductor (CMOS) based imagers. This is mainly because CMOS-based image sensors oer the potential opportunity to integrate low-power signal processing circuitry on-chip and hence reduce component and packaging cost. There is also great demand for wide dynamic range, high ll-factor and high resolution image sensors in some applications such as spectroscopy and ngerprint sensors. These specic applications employ scanning and swiping methods to capture images and hence a linear image sensor is preferred to area format image sensor. Digital interface of the imager chip is essential to overcome system level issues such as signal integrity. To implement digital interface to the imager chip requires an on-chip analog to digital converter. This research presents a new linear image sensor architecture
and circuit techniques that lead to low p ower, wide dynamic range, high ll-factor and high resolution linear image sensor with digital interface. The proposed circuit design is based on a standard 0:4m CMOS process to further reduce cost of the imager chip.

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