65 nm CMOS devices for Low Power Applications

FREE-DOWNLOADK Bailey, KS Gurumurthy, CA Bulucea and Computers in , 2010
This paper attempts to analyze the performance of 65 nm CMOS device structures for low power applications. It indicates that the historical trend of scaling of MOS devices can be sustained by innovative CMOS Structures such as Ultra-thin body SOI devices and multiple gate MOSFETS (such as FinFETS), that can withstand the adverse effects of Scaling. A particular issue of great concern in logic design is the power dissipation. For high- performance logic with increased leakage currents, chip static power dissipation is expected to become a bottleneck to meet aggressive targets for performance scaling. Innovations in circuit design and architecture for performance management as well as utilization of multiple transistors on chip are required for chip design. Multiple transistors having different threshold voltages (Vt) are used selectively with the low Vt, high leakage devices being used mainly in the critical paths and higher Vt, lower leakage devices being used in the rest of the chip area to control static power dissipation. This paper presents the low static power dissipation CMOS devices at 65 nm technology node and compares the performance of SOI CMOS with the conventional planar Bulk CMOS and establishes that SOI CMOS is better suited for low stand-by power applications. A low leakage current of 0.2 pA/mm for NMOS and 0.1 pA/mm for PMOS was observed for SOI devices at a supply voltage of 1.5V as compared to 10nA/mm for bulk CMOS devices at a supply voltage of 1.2V.