A Frequency Compensation Scheme for LDO Voltage Regulators
A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5- m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.
POWER management is a very important issue in portable electronic applications. The need for multiple on-chip voltage levels makes voltage regulators a critical part of an electronic system design. Portable electronic devices like cell phones require very efficient power management to increase the battery life whereas high-speed microprocessors need stable voltages that can supply fast varying currents on the order of few amperes . Low supply voltage noise is also an important requirement for noise sensitive RF circuits that are integral parts of all portable electronic devices. The choice of a voltage regulator for a given application offers numerous design tradeoff considerations. While switch mode regulators provide efficiencies that can reach more than 90% in many practical realizations, they are costly in terms of silicon area, and the magnetic elements are bulky and cause electromagnetic interference (EMI). Moreover, the output voltage ripple and output noise of switching regulators might not be acceptable for several applications such as critical RF circuits. On the other hand, linear regulators have very small output voltage ripple, are compact, have low output noise, and are stable with varying loads. However, linear regulators have lower efficiency that depends on the dropout voltage, which is defined as voltage difference between unregulated supply voltage and regulated output voltage. In many applications, a switching regulator is Fig. 1. Typical LDO voltage regulator. cascaded with a linear regulator to reduce the voltage ripple and improve the stability of the overall system . The minimum permissible dropout voltage of a linear regulator defines the maximum achievable efficiency. The emphasis on efficiency has made low dropout (LDO) regulators the most popular class of linear regulators. But this increase in efficiency is achieved at the cost of a compromise in stability of the regulator. LDO regulators have high output impedance; this impedance, along with the load capacitance, creates a low frequency pole and decreases the overall phase margin. This paper gives an overview of stability problems in LDO voltage regulators, reviews some of the solutions that are being used to overcome this problem, and presents a modified LDO voltage regulator topology. Although the compensating circuit is very simple, the proposed topology successfully overcomes the problem of stability without significantly increasing the power consumption or die area. Both transient response and noise performances are also improved. Transistor level implementation of the design is realized in 0.5- m digital CMOS process, fabricated through the MOSIS service, to demonstrate the feasibility of the proposed solution.