A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65 phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35- m twin-well CMOS process. The proposed LDO dissipates 20- A quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1- F output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

POWER management is essential in all battery-powered portable devices such as cellular phones and PDAs in order to reduce the standby power and prolong the battery runtime. Low-dropout regulators (LDOs) are one of the most critical power management modules, as they can provide regulated low-noise and precision supply voltages for noise-sensitive analog blocks. With the widespread proliferation of modern portable devices, ever more stringent performance requirements of the LDO are needed. First, low dropout voltage across the pass device of the LDO is required provide high power effi- ciency. In addition, the increased level of integration in portable devices not only demands the LDO to deliver high load current, but also requires the no-load quiescent current of the LDO to be minimized for improving the current efficiency [1]. Good load transient response with small output-voltage variation including overshoots and undershoots upon load switching is critical to prevent an accidental turn off or resetting of the portable device. These four major performance requirements of the LDO, including low dropout voltage, high output current, low no-load quiescent current, and small output transient undershoots and overshoots are, however, difficult to achieve simultaneously. In LDO design, the ability to source high load current while achieving low dropout voltage requires the use of a large size pMOS transistor as the pass device. In addition to the low-frequency dominant pole generated by the output capacitor, the large gate capacitance of the pMOS pass device creates another low-frequency non-dominant pole within the unity-gain frequency of the regulation loop, thereby degrading stability. Different approaches have been reported to address this issue . In , an emitter-follower has been adopted as a voltage buffer to drive the pMOS pass device. The low output resistance of the emitter-follower allows the pole at the gate of the pass device to be pushed beyond the unity-gain frequency of the LDO regulation loop. The reported LDO dissipates low quiescent current, while sourcing the maximum load current of 50 mA [1]. However, if the LDO is required source a larger load current (e.g., 100 mA or more), a much larger pass device with larger gate capacitance is needed. The current dissipation of the emitter-follower thus needs to be greatly increased to further lower its output resistance at the gate of the pass device for maintaining loop stability. Instead of dissipating large quiescent current in the voltage buffer to achieve loop stability, the approach of creating a low-frequency left-half-plane (LHP) zero has been widely employed, which provides positive phase shift to compensate for the negative phase shift due to the low-frequency non-dominant pole . The low-frequency LHP zero can be generated by either adding a resistor in series with the output capacitor (or the intrinsic equivalent series resistor (ESR) of the output capacitor), namely ESR zero , or relying on frequency compensation through a voltage-controlled current source. However, the exact pole-zero cancellation within the unity-gain frequency of the LDO regulation loop is difficult to achieve under the full range of the load current. The incomplete pole-zero cancellation may lead to instability of the LDO in the worst condition. Small pole-zero frequency mismatch within the unity-gain frequency can degrade the quasi-linear transient settling behavior, of the LDO upon load switching. Even worse, if the ESR zero approach is adopted, the resistor leads to large output overshoots and undershoots during massive load-current step changes especially

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