An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes
A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0–100 kS/s and 0–200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 W from a 1-V supply. The ADC’s CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by selftiming the bit-decisions. Prototyped in a 0.18- m, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively.
WIRELESS sensor networks offer a sophisticated platform for environment observation. The vision of a micro-sensor network includes dense, intelligent nodes that are energy-autonomous and that operate and are deployed in an ad hoc manner. Nodes are capable of self-organizing into a collaborative network, and subsequently benefit from spatial diversity through data sharing and multi-hop connectivity . Such networks have broad applications ranging from military surveillance, reconnaissance, and damage assessment to environmental forest fire detection [3] and industrial process monitoring.
The design of sensor node hardware is constrained by several factors. To be energy-autonomous, nodes must be powered entirely by an energy harvesting source. This places demanding, low-energy requirements on the constituent circuits. Ad hoc deployment and operation requires that nodes be fault tolerant and able to adapt to unpredictable environments and network characteristics. Finally, ubiquity places a cost constraint on nodes, reducing their acceptable price per unit to a few cents. Fundamentally, the architecture of an intelligent sensor node consists of an analog-to-digital converter (ADC), a digital signal processor (DSP), and a short range radio. This paper describes the design of an ultra-low-power ADC suitable for sensor nodes [4]. In this context, the ADC has a maximum resolution of 12 bits and a sampling rate of up to 100 kS/s, enabling the conversion of signals with the dynamic range and frequencies expected during environment monitoring. However, since both the performance demands and energy budget are time-varying and unpredictable, the ADC also has a low-power 8-bit mode with a maximum sampling rate of 200 kS/s. Further, the sampling rate can be reduced arbitrarily for linear power savings in both resolution modes. Both oversampling and successive approximation register (SAR) architectures are notable for achieving these specifications at the lowest power levels. As resolutions increase beyond 8 bits, oversampling converters have shown to be the most efficient and have the added advantage of reduced anti-aliasing requirements. In sensor applications, however, events occur sporadically, and the nodes might acquire data only once before having to react. As a result, general Nyquist acquisition is preferred. In this design, the SAR architecture is used, and techniques are developed to efficiently increase the resolution to 12 bits.
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