10-bit SAR ADC With a Monotonic Capacitor Switching Procedure
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13- m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a ﬁgure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 265 m
SUCCESSIVE approximation register (SAR) analog-todigital converters (ADCs) require several comparison cycles to complete one conversion, and therefore have limited operational speed. SAR architectures are extensively used in low-power and low-speed (below several MS/s) applications. In recent years, with the feature sizes of CMOS devices scaled down, SAR ADCs have achieved several tens of MS/s to low GS/s sampling rates with 5-bit to 10-bit resolutions –. Although ﬂash and two-step ADCs are preferred solutions for low-resolution high-speed applications, time-interleaved – and multi-bit/step  SAR ADC structures have been demonstrated as feasible alternatives. Medium-resolution time-interleaved SAR ADCs suffer from channel mismatch . Interleaved ADCs must use digital calibration or post-processing  to achieve sufﬁcient performance. For single-channel architectures, the non-binary  and passive charge sharing ,  architectures work at several tens of MS/s and medium resolution (8 to 10 bits) with excellent power efﬁciency and small area.
An ADC with a medium sampling rate (a few tens to hundreds of MS/s) and a medium resolution is a necessary building block for 802.11/a/b/g wireless networks and digital TV applications where pipelined ADCs are extensively used. However, the pipelined architecture requires several operational ampliﬁers, which results in large power dissipation. Moreover, the restrictions for advanced CMOS processes make high performance ampliﬁer design challenging. Drain-induced barrier lowering results in limited gain in short channel devices. Reduced supply voltage also limits the signal swing. With a limited signal swing, the sampling capacitance must be large enough to achieve a high signal-to-noise ratio (SNR), which leads to large current consumption. However, in SAR architectures, no component consumes static power if preampliﬁers are not used. A SAR ADC can easily achieve a rail-to-rail signal swing, meaning that a small sampling capacitance is sufﬁcient for a high SNR. The conversion time and power dissipation become smaller with the advancement of CMOS technologies. Since SAR ADCs take advantage of technological progress, for some high-conversion-rate applications, power- and area-ef- ﬁcient SAR ADCs can possibly replace pipelined ADCs in nanometer scaled CMOS processes. In SAR ADCs, the primary sources of power dissipation are the digital control circuit, comparator, and capacitive reference DAC network. Digital power consumption becomes lower with the advancement of technology. Technology scaling also improves the speed of digital circuits. On the other hand, the power consumption of the comparator and capacitor network is limited by mismatch and noise. Recently, several energy-efﬁcient switching methods have been proposed to lower the switching energy of the capacitor network. The split capacitor method  reduces switching energy by 37%, and the energy-saving method  reduces energy consumption by 56%. Although these methods reduce the switching energy of capacitors, they make the SAR control logic more complicated due to the increased number of capacitors and switches, yielding higher digital power consumption
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