fpga-field programmable gate arrays-research papers-2012 section 14





A Modular Processor Architecture for High-Performance Computing Applications on FPGA
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F Mayer-Lindenberg ,elrond.informatik.tu-freiberg.de
Abstract. This paper presents the architecture of an embedded processor for numeric
applications that is tailored to the resources of current FPGA chips but not limited to FPGA
based applications. The architecture implements several non-standard and even novel 

 Applications Of ADC In FPGA Implementation Of LMS Algorithm For Audio Applications
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SM Sakhare, SS Godbole, SB Pokle ,ijetae.com
Abstract-Adaptive filtering techniques are used in a wide range of applications. Adaptive
noise canceller is one of the most interesting applications for adaptive filters, especially for
the Least Mean Square (LMS) algorithm, due to its strength and calculus simplicity. Noise 

 An FPGA Based a Digital Circuit Design for Route Optimization
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IA Hashim
ABSTRACT Route optimization is searching problem to find the shortest path from starting to
end point within certain criteria. In this paper, a digital circuit design implementation was
presented according to the Dijkstra algorithms and with new digital technology. The 

 Implementation of Fault Tolerant Method Using BCH Code on FPGA
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VP Mahadevaswamy, SL Sunitha ,International Journal of Soft Computing
Abstract—The Fault tolerance degradation is the property that enables a system (often
computer-based) to continue operating properly in the event of the failure of (or one or more
faults within) some of its components. To designing a new 32-bit Arithmetic Logic Unit ( 

 FPGA-Based RONJA Twister
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J Matyáš ,acmbulletin.fiit.stuba.sk
Abstract RONJA is an open-source device which utilizes a visiblelight beam for establishing
a wireless point-to-point data link. It is designed to operate in 10Mbps full-duplex mode over
a distance up to 1.4 km. This paper deals with one of RONJA modules referred to as 

 FT-UNSHADES2: A Platform for early evaluation of ASIC and FPGA dependability using partial reconfiguration
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Abstract—Fault injection is a widely accepted method for the evaluation of device and
system reliability, by mean of dynamic analysis of a digital circuit implemented in a FPGA. A
set of test vectors is applied and output vectors are monitored while a number of faults are 

 Simplified FPGA Design with Robei
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G Wu ,elrond.informatik.tu-freiberg.de
Abstract–Robei is a tiny cross platform FPGA design tool that aims to simplify design
procedure, transparent intellectual properties and reduce complexity. It makes FPGA design
like playing with boxes by breaking down hardware into three basic elements: module, 

 Several AES Variants under VHDL language In FPGA
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S Arrag, A Hamdoun, A Tragha, S eddine Khamlich ,2012
Abstract This paper provides four different architectures for encrypting and decrypting 128 bit
information via the AES. The encryption algorithm includes the Key Expansion module
which generates Key for all iterations on the fly, Double AEStwo-key triple AES, AESX and 

 FPGA BASED AN ADVANCED LUT METHODOLOGY FOR DESIGN OF A DIGITAL FILTER
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GS Bala, AR Krishna, S Balaji
Abstract The present manuscript proposes an advanced methodology based on which the
LUT is modeled through which an FIR filter is designed for efficient area utilization. As it is a
known fact that most of the DSP processors concerned with the multiply and accumulate 

 FPGA Based Embedded Multiprocessor Architecture
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SS Jadhav, CN Bhoyar
Abstract-Multiprocessor is a typical subject within the Computer architecture field of scope. A
new methodology based on practical sessions with real devices and design is proposed.
Embedded multiprocessor design presents challenges and opportunities that stem from 

 FPGA Implementations of Single-Multiplier Digital Sine-Cosine Wave Generators
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JM Abdul-Jabbar, NN Qaqos ,alrafidain.engineering-coll-mosul.
Abstract This paper presents four different realizations of single-multiplier sine-cosine
generators based on second-order digital filter structure. FPGA implementations of these
four realizations are carried out on FPGA Spartan-3E Kit. Implementation results are 

 Design and FPGA implementation of High Speed Linear FIR low pass filter using Kaiser Window function
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M Badiger, M Prameela
Abstract-Real time signal processing can be achieved in three different ways namely
window method, frequency sampling and using optimal filters. Among these, the window
technique is comparatively better in terms of eliminating the ringing effects at the band 

 Implementation Of Path Length Control For RLG Using FPGA
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P Pasula, RB Natha ,2012
Abstract: Ring Laser Gyro (RLG) is used to sense angular information accurately and
precisely. In a RLG, an optical ring is formed, and two laser beams are directed around the
ring in opposite directions. When the beams are combined, rotation of the ring appears as 

 Performance Evaluation of Hybrid Reconfigurable Computing Architecture over SymmetricalFPGA
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Abstract For last few decades, reconfigurable devices have been extensively used in digital
systems. Reconfigurable computing using FPGA devices provide a method to utilize the
available logic resources on the chip for various computations. The basic ability of 

 FPGA BASED INDIRECT POSITION DETECTION AND SPEED CONTROL OF PMBLDC MOTOR USING VIRUTAL INSTRUMENTATION
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LL EE
ABSTRACT Recently, the brushless dc (BLDC) motor is becoming popular in various
applications because of its high efficiency, high power factor, high torque, simple control,
and lower maintenance. Moreover, reducing of the drive components is more attractive for 

 Implementation of Embedded Multiprocessor Architecture Using FPGA
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MSS Jadhav, CN Bhoyar
Abstract—Embedded multiprocessor design presents challenges and opportunities that
stem from task coarse granularity and the large number of inputs and outputs for each task.
We have therefore designed a new architecture called embedded concurrent computing ( 

 Embedded Intelligence on Chip: Some FPGA-based design experiences
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The following FPGA-based (Field Programmable Gate Array) experiences stem from a
broader line of research investigating methodologies for scaling cognitive/intelligent
architectures into limited-resource implementations. Some of these architectures were 

 iDEA: A DSP Block Based FPGA Soft Processor
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Abstract—This paper presents a very lean DSP Extension Architecture (iDEA) soft processor
for Field Programmable Gate Arrays (FPGAs). iDEA has been built to be as lightweight as
possible, utilising the run-time flexibility of the DSP48E1 primitive in Xilinx FPGAs to serve 

 LegUp: An Open Source High-Level Synthesis Tool for FPGA-Based Processor/Accelerator Systems
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A CANIS, J CHOI, M ALDHAM ,legup.eecg.utoronto.ca
It is generally accepted that a custom hardware implementation of a set of computations will
provide superior speed and energy-efficiency relative to a software implementation.
However, the cost and difficulty of hardware design is often prohibitive, and consequently, 

 An Implementation of WCDMA Rake Receiver on FPGA using VHDL Used In 3G Wireless Communications
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K Sahu, H Prajapati
Abstract 3G mobile communications is advanced and emerging technology in the field of
wireless communication also providing facilities like multimedia accessing, internet services,
higher capacity of data rates and multiple services for same connection. The Rake 

 An FPGA-based supercomputer for statistical physics: the weird case of Janus
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M Baity-Jesi, RA Banos, A Cruz, LA Fernandez ,eweb.unex.es
Abstract In this chapter we describe the Janus supercomputer, a massively parallel FPGA-
based system optimized for the simulation of spin-glasses, theoretical models that describe
the behavior of glassy materials. The custom architecture of Janus has been developed to 



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