fpga-field programmable gate arrays-research papers-2012 section 13

A GPGPU Implementation of Approximate String Matching with Regular Expression Operators and Comparison with Its FPGA Implementation
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Y Utan, M Inagi, S Wakabayashi, S Nagayama ,elrond.informatik.tu-freiberg.de
Abstract—In this paper, we propose an efficient GPGPU implementation of an algorithm for
approximate string matching with regular expression operators, originally implemented on
an FPGA, and compare the GPGPU, FPGA and CPU implementations by experiments. 

 FPGA-Realization of a Motion Control IC for XY Table
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YS Kung, TY Tai ,cdn.intechopen.com
The development of a compact and high performance motion controller for precision XY
table, CNC machine etc. has been a popular field in literature (Goto et al., 1996; Wang &
Lee, 1999; Hanafi et al., 2003). In position control of XY table, there are two approaches to 

 Evolvable Hardware FPGA-based platform for Autonomous Fault-tolerant Systems
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J Mora, A Otero, Á Gallego, R Salvador, E de la Torre
Evolvable Hardware (EH) is a technique that consists on the use of reconfigurable hardware
devices whose configuration is controlled by an Evolutionary Algorithm (EA). In this
demonstration we show an EH platform where the full system is implemented in the FPGA. 

 FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme
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D Sowjanya, KNH Srinivas, PV Ganapathi ,International Journal
ABSTRACT In this paper, a scheme for the design of area efficient and high speed pipeline
VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using
lifting scheme is proposed. The main focus of the scheme is to reduce the number and 

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KM Al-Aubidy, F Ra’ed, AS Ala’a ,basketballpro.net
ABSTRACT FPGA technology offers the potential of designing high performance systems at
low cost. FPGAs have been used for many computational tasks, and this paper presents the
microoperation simulation of a basic computer and its implementation on an FPGA. Also, it 

 A High Speed Open Source Controller for FPGA Partial Reconfiguration
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Abstract—Partial Reconfiguration (PR) is an advanced technique, which improves the
flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by
overwriting parts of the configuration memory. PR is an important enabler for 

 FPGA Implementation of Fuzzy Inference System for Embedded Applications
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KM Al-Aubidy ,
Abstract:-Implementing algorithms in software limits the performance of real-time systems,
since the data is processed serially. The new generation of FPGAs with embedded
processors are attracting the interest of the real-time applications. With enhanced 

 FPGA Implementation of Multi-alphabet Arithmetic Coding using Rotating Intervals
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R Adluri, GS Babu, P Daniel
ABSTRACT We present a modified AC scheme for multi-alphabet that offers both encryption
and compression. The system utilises an arithmetic coder in which the overall length within
the range [0, 1] allocated to each symbol is upheld, but the conventional assumption that 

 Developers Nurturing FPGA based Soft IP Cores for Catering the Needs of Advanced Image Processing Applications–A Review
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N SO, RK Kamat ,ijetae.com
Abstract—Proficient and high performance image processing systems are in demand never
than ever before due to the all perverseness of the multimedia technology being penetrated
in almost all the fields. The core of such systems is the signal and image processing 

 Tx/Rx: Generation and Correlation of a Costas Array FM Code Using FPGA Spatran-3 Technology
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TR Saeed
ABSTRACT This paper describes a real time generation and correlation of Costas array FM
code pulse compression using Field Programmable Gate Array (FPGA) for implementation,
which provides the flexibility, reconfigure ability and reprogram ability. This 

 A Low Power Asynchronous FPGA With Power Gating and Dual Rail Encoding
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K Naveena, N Kirthika ,ijcset.net
Abstract—A low power Asynchronous FPGA with LEDR encoding and 4-Phase dual Rail
Encoding is designed in this paper. 4-Phase Dual Rail encoding is to achieve small area
and LEDR encoding is to get high throughput and low power. LEDR encoding is done at 

 Circuit Partitioning Methods for FPGA-based ASIC Emulator using High-speed Serial Wires
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K Takahashi, M Amagasaki, M Kuga, M Iida ,sasimi.jp
Abstract—We are studying FPGA-based ASIC emulator via high-speed serial
communication. In this emulator, there are restrictions on placement of the FFs on FPGA and
we have to reduce replicated logic gates and replicated input terminal when partitioning 

 FPGA Implementation of Digit-Serial Architecture for Various Digit-Size and Wordlength in Viterbi Decoder
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Abstract-Convolutional code is an essential Forward Error Correcting (FEC) code for many
wireless communication systems. Viterbi decoder is an optimal algorithm for decoding a
convolution code. The design of an efficient Integrated Circuit (IC) in terms of power, area 

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B Senthilkumar, G Umamaheswari
In medical image processing, noise removal is the challenging task. Removal of noise using
the existing methods like Median Filter (MF), Center Weighted Median Filter (CWMF), Rank
Condition Rank Selection Filter (RCRSF) and SMF Selective Median Filter (SMF) provides 

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MKS Patil, GD Salunke, MBL Mahajan, AS Hiwale
Abstract To successfilly transmit data over any network, a protocol is required to manage the
flow or pace at which the data is transmitted. This protocol is defined in Layer 2 of OS1
(Open Systems Interconnection) model. High-level Data Link Control (HDLC) is the most 

 Estimation of HW/SW Cost Parameters in Altera FPGA Design Environment
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Abstract:-This paper explains the method for obtaining Hardware/Software (HW/SW) cost
parameters such as hardware area, hardware time, software area and software time using
Altera FPGA design environment. HW/SW partitioning of FFT and JPEG FDCT are derived 

 FPGA-Accelerated Isotope Pattern Calculator for Use in Simulated Mass Spectrometry Peptide and Protein Chemistry
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C Pascoe, D Box, H Lam, A George ,plaza.ufl.edu
Abstract—Over the past 20 to 30 years, the analysis of tandem mass spectrometry data
generated from protein fragments has become the dominant method for the identification
and classification of unknown protein samples. With wide ranging application in numerous 

 Performance Evaluation for RVE-based FPGA Acceleration of Genetic Sequence Alignment
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L HASAN, H ZAFAR ,news.usindh.edu.pk
Abstract: In this paper, Recursive Variable Expansion (RVE)-based Field-Programmable
Gate Array (FPGA) acceleration of genetic sequence alignment and its comparison with
traditional systolic array based acceleration is presented. The paper evaluates 

 FPGA Based Muzzle Velocity Measurement System
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K Lakshmi, KS Kumar, AVV Satyanarayana ,ijetae.com
Abstract—Muzzle velocity is the initial velocity of a projectile as it comes out. A novel
measurement method which can measure velocity of projectile by measuring its travel time.
It mainly contains the laser sources and laser detectors those are employed to measure 

 FPGA Based Accelerator for Bioinformatics Haplotype Inference Application
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N Harb, MAR Saghir, Z Dawy, C Valderrama ,elrond.informatik.tu-freiberg.de
Abstract—1 Hardware accelerators have been used to accelerate various bioinformatics
applications without altering their accuracy. These accelerators are used to speed up
sophisticated algorithms where powerful computational techniques are used to analyse, 

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MMD Tayade, PD Gawande
ABSTRACT Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) is a
suitable solution to implementation of high speed data transmission in ultra wideband
spectrum by dividing the spectrum available into multiple bands. The baseband of 

 Boosting Dynamics of AC Machines by using FPGA-Based Controls
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O Buchholz, S Mathapati, J Böcker ,wwwlea.uni-paderborn.de
Abstract The main focus of the following contribution is to point out the advantages of Field
Programmable Gate Arrays (FPGAs) as a realization platform for AC machine controls in
comparison to state-of-the-art Digital Signal Processor (DSP) based controls. Initially 

 Fault Detection And Diagnosis In SRAM Based FPGA Using BIST
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ABSTRACT This paper presents a built-in self-test (BIST) design for fault detection and fault
diagnosis of static-RAM (SRAM)-based field-programmable gate arrays (FPGAs). The
proposed FPGA BIST structure can test both the interconnect resources [wire channels 

 Visual Exploration of Simulated FPGA Architecures in Odin II
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Abstract Field Programmable Gate Array (FPGA) research became more and more important
during the last decades. The FPGA technology is being used in many fields and offers the
main features scalability, flexibility and the low costs of prototyping. The functionality of 

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NV Quynh, T Hanh, TTT Tam, LP Truong ,lhu.edu.vn
Abstract: Permanent magnet synchronous motor (PMSM) was applied so much in the
accurate manufacturing industry. Almost all of automatic systems included optical encoder
for velocity measurement. The price of optical encoders is very expensive, so some 

 FPGA Based Area And Throughput Implementation of JH And BLAKE Hash Function
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V Doshi, R Arya, RK Yadav
Abstract Implementation of area and throughput of the main building block (compression
function) for two SHA-3 candidates BLAKE and JH hash function. The National Institute of
Standards and Technology (NIST) has started a competition for a new secure hash 

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S Khurana, K Kaur ,ijettcs.org
Abstract: This paper primarily deals with the construction of arithmetic Logic Unit (ALU) using
Hardware Description Language (HDL) using Xilinx ISE 9.2 i and implement them on Field
Programmable Gate Arrays (FPGAs) to analyze the design parameters.. ALU of digital 

 Reconfigurable IEEE1451-FPGA based weblab infrastructure
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Abstract-Weblabs are spreading their influence in Science and Engineering (S&E) courses
providing a way to remotely conduct real experiments. Typically, they are implemented by
different architectures and infrastructures supported by Instruments and Modules (I&Ms)