fpga-field programmable gate arrays-research papers-2012 section 9
VLSI Implementation of a 2×2 MIMO-OFDM System on FPGA
free download
R Premalatha, M Shanthi
Abstract—Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-
OFDM) technology is an attractive transmission technique for wireless communication
systems with multiple antennas at transmitter and receiver. The core of this technology is
Implementation of Multiplierless Ramanujan Ordered Number DCT on FPGA
free download
KS Geetha, U Kumari
Abstract An efficient implementation of discrete cosine transform (DCT) computations is
presented based on the Ramanujan ordered number DCT (RDCT), a fast multiplierless DCT
algorithm. Due to the simple form of the factorized matrices, the derived architecture can
Hardware Design of Image Channel Denoiser for FPGA Embedded Systems
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O SHARIFI-TEHRANI ,red.pe.org.pl
Abstract. In this article an FPGA-based image channel denoiser using a 1D-standard-LMS
algorithm is proposed. The designed core is written in VHDL93 language as basis of 1D-FIR
adaptive filter. The proposed core is FPGA-brand-independent, hence can be ported on
FPGA IMPLEMENTATION OF FLOATING POINT RECIPROCATOR
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B Sujatha, DR Rao
ABSTRACT In this paper an efficient FPGA implementation of a reciprocator for both IEEE
single-precision and double-precision floating numbers is presented. This method is based
on the use of look-up-tables (LUTs) and partial block multipliers. Previously the LUTs and
High Level Library for fast developing pipelined data paths on FPGA: Case study of tool path computation
free download
JP Martinez, AJ Morenilla, SC Asensi, JLS Romero ,jornadassarteco.org
Resumen—The algorithms used for tool path computation demand a higher computation
performance, which makes the implementation on many existing systems very slow or even
impractical. Hardware acceleration is an incremental solution that can be cleanly added to
An FPGA based Accelerator for Encrypted File Systems
free download
ABSTRACT In this work, the possibility of application of an AES coprocessor to increase the
performance of encrypted file systems is examined. A brief description of an architecture
based on an FPGA connected to a GPPU using PCI Express is followed by the preliminary
Implementation of Frequency Down Converter using Multiplier free filter on FPGA
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KS Sushmitha, GV Kumari ,ijettjournal.org
Abstract—In a Communication system, especially in some applications where confidential
data is to be communicated, wideband of signals are used. Also the bandwidth of the signal
is frequently varied so that it is undetectable by the third person. In such cases to detect
Remote FPGA Lab for Enhancing Learning of Digital Systems Accepted: Camera Ready Editing in Progress
free download
F MORGAN, S CAWLEY ,elucidare.co.uk
Learning in digital systems can be enhanced through applying a learn-by-doing approach
on practical hardware systems and by using web-based technology to visualise and animate
hardware behaviour. The authors have reported the web-based Remote FPGA Lab (RFL)
Implementation of Data Encryption Algorithm For FPGA Based Real-Time Data Security Applications
free download
S Manikonda, S Tandle ,irnetexplore.ac.in
Abstract-Data security is an issue in Communication Systems and cryptographic algorithms
are essential parts in network security. Data must be encrypted before it is transmitted. In
several high speed real time data encryption schemes, we need hardware implementation
FPGA Implementation of ADPLL with Ripple Reduction Techniques
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M Kumar, K Lata
ABSTRACT In this paper FPGA implementation of ADPLL using Verilog is presented.
ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For
simulation ISE Xilinx 10.1 CAD is used. Vertex5 FPGA (Field Programmable Gate Array) is
FPGA Based Design and Implementation of Datapath Controllers for Low Power Pipelined 32-Bit RISC Stored Program Machine
free download
P Bhosle, HK Moorthy ,iosrjournals.org
ABSTRACT: This paper presents the design and implementation of data path controllers, for
low power pipelined 32 bit High performance, RISC Stored Program Machine using Verilog.
The various blocks include the Fetch, Decode, Execute, Memory Read/Write Back to
ELECTROCARDIOGRAM (ECG) SIGNAL PROCESSING ON FPGA FOR EMERGING HEALTHCARE APPLICATIONS
free download
MR KUMAR
Abstract-In this project an ECG signal processing module will be implemented in VHDL on
FPGA platform. The digital filtering will be carried out with low pass FIR architecture. Filters
shall filter the 50 Hz coupled noise and other high frequency noises. The filtered signal is
FPGA-Based Hybrid GA-PSO Algorithm and Its Application to Global Path Planning for Mobile Robots
free download
HC HUANG
Abstract. This paper presents an FPGA-based (field-programmable gate array) hybrid
metaheuristic GA (genetic algorithm)-PSO (particle swarm optimization) algorithm for mobile
robots to find an optimal path between a starting and ending point in a grid environment.
SURVEY OF PROTECTION TECHNIQUES FOR IP CORES IMPLEMENTED IN FPGA
free download
L Sridhar, VL Prabha ,rspublication.com
ABSTRACT In the past two decades, the continuous advancement in semiconductor
manufacturing has made the Field Programmable Gate Arrays (FPGA) an appealing vehicle
for a number of applications and rapid system prototyping. The most impressive
AREA OPTIMIZED FPGA IMPLEMENTATION OF ADAPTIVE BEAMFORMER
free download
H Kaur, PS Jassal
Abstract—Quadratic Rotation decomposition (QRD) based recursive least squares (RLS)
algorithm can be used in variety of communication applications and its low complexity
implementation can be of interest. In this paper we have presented an application of QRD
Transmitter Implementation Using DS-CDMA Technique in FPGA Using Verilog HDL
free download
TS Mahbub, S Ahmed, IR Rokon
Abstract-The DS-CDMA is expected to be the major medium access technology in the future
mobile systems owing to its potential capacity enhancement and the robustness against
noise. DS-CDMA is a type of spread-spectrum communication system in which multiple
FPGA Based High Performance Optical Flow Computation Using Parallel Architecture
free download
N Devi, V Nagarajan ,International Journal of Soft Computing
Abstract-The proposed work describes a highly parallel architecture for high performance
optical flow computation. This system implements the efficient Lucas and Kanade algorithm
with multi-scale extension for the computation of large motion estimations. This work deals
A Self-Organization Maps Approach to FPGA Placement
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MAYTM Iida, MKT Sueyoshi ,sasimi.jp
Abstract—Cell placement is an important phase of current Field Programmable Gate Array
(FPGA) circuit design. However, this placement problem is NP-hard. Although
nondeterministic algorithms such as Simulated Annealing (SA) are successful in solving
Implementation of Power Management Specs in Low Power Devices using FPGA
free download
BS Supritha, C Suresh ,irnetexplore.ac.in
Abstract: This paper explains the power management in low power devices whose
specifications are verified in the Spartan 3A FPGA. Power Management Integrated Circuit
(PMIC) is designed to manage and supply the power to low power platforms like Tablet
Implementation Issues of Kohonen Self-Organizing Map Realized on FPGA
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W Pedrycz, PA Farine ,dice.ucl.ac.be
Abstract. Presented are the investigations showing an impact of the length of data signals in
hardware implemented Kohonen Self-Organizing Maps (SOM) on the quality of the learning
process. The aim of this work was to determine the allowable reduction of the number of
Mathematical Aspects of the Implementation of Particle Filters on FPGA
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J Schönefeld, DPF Möller ,seth.asc.tuwien.ac.at
Abstract: Particle filters are a type of Bayesian filters commonly used for system state
estimation such as tracking and localization applications. Tracking and localization are
important tasks for autonomous robots, and particle filters are particularly well suited to
DESIGN AND IMPLEMENTATION OF PCM DECOMMUTATOR ON A SINGLE FPGA
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G PRASAD, N VASANTHA
Abstract: After frame synchronization, individual measurands are identified according to the
frame location. The decommutator identifies and extracts embedded asynchronous data
stream (EADS) words. Thus PCM Decommutator is a very crucial subsystem in the
An FPGA Based Microblaze Soft Core Architecture for 2D-LIFTING
free download
K Priyanka, M Pradeep ,iosrjournals.org
ABSTRACT: In this paper we propose a technique for software-implementation of an lifting
with the goal of getting a customizable lifting DWT-core which can be used as a module in
implementing a bigger system irrespective of ones choice of implementation platform.
A FPGA Implementation of a RISC Processor for Computer Architecture
free download
VR Wadhankar, V Tehre ,IJCA Proceedings on National , 2012
ABSTRACT This paper is concerned with the design and implementation of a 32bit Reduced
Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs).
We are designing the processor with VHDL and the simulation using Altera Quartus Plus2,
FPGA REAL TIME ACCELERATION FOR DISCRETE
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J STANDARD
ABSTRACT In recent years video and image compression have became very required. The
availability of powerful software design tools is a fundamental requirement to take
advantage of the many advanced and specialized resources included in the latest devices
High Speed DWT Processor Implementation in FPGA
free download
AF Mulla, NN Mane, RC Wagavekar, RS Patil ,ijetae.com
Abstract-This paper presents a high speed and area efficient DWT processor VLSI based
design for Image Compression applications. In this proposed design, pipelined partially
serial architecture has been used to enhance the speed along with optimal utilization and
Pulse Width Modulation Implementation using FPGA and CPLD ICs
free download
JI Tamboli, SR Jagtap, AR Sutar
Abstract-Pulse width modulation (PWM) has been widely used in power converter control.
Most high power level converters operate at switching frequencies in excess of 1 MHz at
high power levels can be achieved using the planar transformer technology. PWM control
Yet Another SHA-3 Round 3 FPGA Results Paper
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Abstract. The NIST run SHA-3 competition is nearing completion. Currently in its final round,
the five remaining competitors are still being examined in hardware, software and for
security metrics in order to select a final winner. While there have been many area and
FPGA Implementation of Different Multiplier Architectures
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S Laxman, D Prabhu, MS Shetty, M Manjula, C Sharma ,ijetae.com
NMIT, Bangalore,Govindapura,Gollahalli NMIT, Bangalore,Govindapura,Gollahalli NMIT,
Bangalore,Govindapura,Gollahalli Abstract-In this paper 2 different multiplier architectures
are implemented in Xilink FPGA and compared for their performance. Here these
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