Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

FREE-DOWNLOAD J Hoentschel, A Wei, M Wiatr , 2008. IEDM 2008.
It has become extremely challenging for EOT scaling to keep pace with gate length reduction in advanced technology generations. This has resulted in non-optimal transistor electrostatic integrity, performance, and reliability tradeoffs. At a given EOT, however, a transistor with an asymmetric channel configuration can offer several advantages in terms of performance and electrostatics . This paper demonstrates that optimized transistors with asymmetric halos and asymmetric source/drain extensions can simultaneously improve drive current, reduce DIBL, reduce drain-side Miller capacitance, and reduce drain-side electric field. Optimized asymmetric transistors have been implemented on the product level, resulting in a substantial overall performance and reliability advantage.