microprocessor research papers 32

microprocessor research papers 32


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Microprocessor protection devices: The present and the future
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Paper presents the analysis of the basic constructive disadvantages of the present day microprocessor-based protective devices (MBR) and offers the basic principles for creating a new MBR that can be used in newly constructed devices.

Using formal specifications to monitor and guide simulation: Verifying the cache coherence engine of the Alpha 21364 microprocessor
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ABSTRACT We describe a technique for verifying that a hardware design correctly implements a protocol. The application of this technique to verifying the cache and memory controllers of the Alpha 21364 EV7 microprocessor against a formal specification of the EV7 cache

Simulation of the MC88000 microprocessor system on a transputer network
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This project investigated the feasibility of building a General Purpose Architecture Simulator on an MIMD transputer network. In the course of this study an Occam2 simulation of the 88100 Reduced Instruction Set micro-processor was developed on an MIMD T800

An inexpensive, microprocessor-based, data logging system
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Efforts to understand and model environmental variables require data sets that track both temporal and spatial changes. Networks of recording instruments or instruments connected to commercially available data loggers can gather these data (eg, Silliman and Booth,

The new SIMD implementation of the Smith-Waterman algorithm on Cell microprocessor
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Algorithms for estimating similarity between two macromolecular sequences are of profound importance for molecular biology. The standard methods utilize so-called primary structure, that is a string of characters denoting the sequence of monomers in hetero-polymer.

Microprocessor prosthetic knees
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During the 1970s, research in the field of computerized knee joints began in the university environment. In the late 1980s and early 1990s, various prosthetic companies began working on the first commercial microprocessor controlled knee joints. The initial

AMD s next generation microprocessor architecture
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AMD s Next Generation Microprocessor Architecture Fred Weber October 2001  24 HyperTransport™ Technology • Next-generation computing performance goes beyond the microprocessor • Screaming I/O for chip-to-chip communication – High bandwidth – Reduced pin count

Understanding microprocessor-based technology applied to relaying
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Page 1. 2009 – January WG I-01 Report ,Understanding microprocessor-based technology applied to relaying i UNDERSTANDING MICROPROCESSOR-BASED  Page 2. 2009 – January WG I-01 Report ,Understanding microprocessor-based technology applied to relaying ii

Microprocessor Design
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Being a computer science or electrical engineering student, you have probably assembled a PC. You have gone out to purchase the motherboard, CPU, memory, disk drive, video card, sound card and other necessary parts. You have assembled them together, and have

Embedded real-time communication protocol development using SDL for ARMmicroprocessor
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INTRODUCTION ith the rising complexity of communication protocols, designers are provided with highly efficient model-based tools to increase the level ofAbstraction at which the developers work. Such tool is SDT of Telelogic, that uses the telecommunication

Methodology and Experience of Simulation-Based Verification of Microprocessor Units Based on Cycle-Accurate Contract Specifications
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ABSTRACT In this paper we describe a methodology and ex-perience of simulation-based verification of microprocessor units based on cycle-accurate contract specifications. Such specifications describe behavior of a unit in the form of preconditions and postconditions

UNUM: A General Microprocessor Framework Using Guarded Atomic Actions
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We present UNUM: the UNified Universal Microprocessor framework. UNUM provides an infrastructure to generate both C and RTL descriptions using the Bluespec hardware description language. The RTL descriptions are leveraged to provide fast simulations via

The Effects of Microprocessor Architecture on Speedup in Distrbuted Memory Supercomputers
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This chapter presents the results from the tests described in Chapter 4. In-depth discussion of these results is reserved for Chapter 6. First we present the results from the three major test programs when utilizing two processors per node. These results are followed by our

Could microprocessor obsolescence be history?
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The predicament of automotive telematics equipment designers, for example, is representative of the problem. Although design and development time scales have shrunk from five years down to two, production is measured in years and the products remain

Self-timed asynchronous architecture of an advanced general purpose microprocessor
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Avid Execution (Ch. 3) requires a wide memory bandwidth to prefetch and decode many instructions concurrently. While a variable length instruction set reduces the number of bytes that need to be fetched from memory, its decoding is difficult and may pose a bottleneck in

microprocessor-based colorimeter
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A block diagram of the instrument is shown in figure 1. Light emittingdiodes (LEDs) are used as the light source because LEDs offer a fixed wavelength, narrow emission profile and low power requirements. Because the band width is narrow, filters are not required. LEDs with

Great moments in microprocessor history
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The evolution of the modern microprocessor is one of many surprising twists and turns. Who invented the first micro? Who had the first 32-bit single-chip design? You might be surprised at the answers. This article shows the defining decisions that brought the contemporary

Fault injection for embedded microprocessor-based systems
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ABSTRACT Microprocessor-based embedded systems are increasingly used to control safetycritical systems (eg, air and railway traffic control, nuclear plant control, aircraft and car control). In this case, fault tolerance mechanisms are introduced at the hardware and

  The action system framework for modelling parallel programs is used to formally specify a microprocessor. First the microprocessor is specified as a sequential program. The sequential specification is then decomposed and refined into a concurrent program using

Microprocessor-controlled small-scale vehicles for experiments in automated highway systems
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FLASH laboratory is a small scale (approximately l/15th) instrumented model of the AHS system and is presently in development [1-8]. In this laboratory, small scale instrumented vehicles are used for experimentation. The laboratory is being developed so that it will

Architecture evaluator s work bench and its application to microprocessor floating point units
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ABSTRACT This paper introduces Architecture Evaluator s Workbench AEWB, a high level design space exploration methodology, and its application to oating point units FPUs. In applying AEWB to FPUs, a metric for optimizing and comparing FPU implementations is

Accurate analysis of single event upsets in a pipelined microprocessor
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Modern processors embed features such as pipelined execution units and cache memories that can not be directly controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are even less suitable for assessing

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