microprocessor research papers 51


 Theoretical system-level model for power-performance trade-off in VLSI microprocessordesign
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M Olivieri ,Workshop on Complexity-Effective Design, 2001 ,vlsi.die.uniroma1.it
Abstract: This contribution provides a quantitative model of the relation between supply
voltage scaling, sustainable cycle time, pipeline depth, instruction level parallelism and
power dissipation. The analysis show that there is an optimal sizing of the target supply 

 One Solution of Task Priority Ordering in Microprocessor Measuring Station
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DR Milivojevic, V Tasic, V Despotovic , Technology and Control, , 2009 ,itc.ktu.lt
Abstract. Microprocessor Measuring Station (MMS) is a type of programmable logic
controller fully developed and designed in Mining and metallurgy institute Bor, Serbia, for
monitoring and process control, mainly in copper production plants. It is based on 

 Granularity of microprocessor thermal management: a technical report
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Abstract Process technology scaling, poor supply voltage scaling and the resultant
exponential increase in power density have made temperature a first-class design constraint
in today’s microprocessors. An interesting question in the context of thermal management 

 An elastic microprocessor core for Xilinx FPGAs
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RE Haskell ,Second IEEE Electro/Information , 2001 ,metis.secs.oakland.edu
Abstract An embedded system based on the use of an FPGA such as the Xilinx Spartan or
4000 series FPGA is typically designed using a hardware description language such as
VHDL. On the other hand an embedded system based on the use of a microcontroller 

 Microprocessor Design Automation: A DNA Based Evolutionary Approach
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N Venkateswaran, A Kumeresh ,Brain Inspired Cognitive , 2006 ,cs.duke.edu
ABSTRACT Process automation has always been one of the prime areas of research.
Evolutionary systems have had an edge over their conventional counterparts as they mimic
the successful natural selection process. A novel evolutionary approach for the 

 Design of a microprocessor based automatic gate
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O Shoewu ,Pacific Journal of Science and Technology, 2006 ,brc.nitk.ac.in
ABSTRACT The work presented here outlines the development of a microprocessor based
automatic gate. The inconveniences encountered in gate operations has called for an
immense search for solutions. The microprocessor based automatic gate offers everything 

 Device Distributed Approach to Expandable Robot System Using Intelligent Device with Super-Microprocessor
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K Okada, A Fuyuno, T Morishita ,Journal of Robotics , 2004 ,jsk.tu-tokyo.ac.jp
This paper describes a device distributed approach to realize a simple, expandable robot
system that enables a number of devices to be attached or added to a built-in robot without
significant changes to software and hardware. The robot system based on a device 

Physical implementation of the 1GHz Godson-3 quad-core microprocessor
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BX Fan, L Yang, JM Wang, R Wang, B Xiao ,Journal of Computer , 2010 ,Springer
Abstract The Godson-3A microprocessor is a quad-core version of the scalable Godson-3
multi-core series. It is physically implemented based on the 65 nm CMOS process. This
174mm 2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a 

 Reconfigurable microprocessor and microcontroller–architectures and classification
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C Siemers ,Proceedings Embedded World 2004 Conference, 2004 ,piv.by
Technical University of Clausthal, Institute for Computer Science, Julius-Albert-Str. 4, D-
38678 Clausthal-Zellerfeld, Germany, siemers| richter@ informatik. tu-clausthal. de Abstract.
Reconfigurable microprocessors and microcontroller are facing their market introduction 

Finding stress patterns in microprocessor workloads
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F Vandeputte ,High Performance Embedded Architectures , 2009 ,Springer
Power consumption has emerged as a key design concern across the entire computing
range, from low-end embedded systems to high-end supercomputers. Understanding the
power characteristics of a microprocessor under design requires a careful study using a 

 Scalable passively mode-locked semiconductor lasers for microprocessor clocking
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JP Siepmann ,Proc. of SPIE Vol, 2006
ABSTRACT The integration of photonic clocking in microprocessors is anticipated to occur
during the 2008-2012 high-volume manufacturing (HVM) cycle. Though photonic clocking
can be achieved through electronic modulation or actively mode-locking a laser, a more 

 Random Test Generators for Microprocessor Design Validation
free download

J Storm ,2006 ,opensparc.net
• Design Verification Process Overview Functional Verification Only> No performance No
timing> No electrical, circuit, power, etc.• Random Instruction Generator Design> Full
Featured Generator Useful in simulation Bootable on hardware• OpenSPARC http:// 

 Using Microprocessor and DSP debug interfaces for manufacturing functional test and diagnosis
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B Fenton ,Etronix conference 2001, 2001 ,intertesttech.com
Abstract As board test access begins to disappear, industry roadmaps [1] predict a move
from traditional in-circuit test methods to automated inspection techniques, JTAG, and
functional test. Although requiring minimal test access, functional testers have a number of 

 Fixed Abrasive Based Hybrid STI CMP Process for High Volume Microprocessor Production in 65nm Technology Node
free download

B Reinhold ,Int. Conf. On Planarization/CMP , 2006 ,planarization-cmp.org
Planarity requirements for the gate module become more and more stringent with the
continued down shrinking of feature sizes. This puts the challenge on the STI CMP process-
as first topography altering step in the process flow-to deliver ultra planar trench features 

 Microprocessor optimization for network protocol implementations
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K Camera, T Tuan ,Berkeley Wireless Research , 1999 ,cs.berkeley.edu
Abstract A popular trend in modern computing is the migration from desktop computing to a
more distributed environment where individual devices communicate with each other over a
network. Such devices, especially those in the wireless domain, are typically limited in 

 Single event effects testing of the Intel Pentium III (P3) microprocessor
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J Howard, K LaBel, M Carts , Event-Effects (SEE , 2002 ,radhome.gsfc.nasa.gov
Many future NASA missions will require extensive on-board computation capability which
raises the issue of availability, cost and capability of radiation hardened or radiation tolerant
microprocessor systems. Radiation hardened computer systems are often costly and are 

 An Illustration of the Benefits of the MIPS® R12000® Microprocessor and OCTANETM System Architecture
free download

I Williams ,1999 ,134.91.82.10
As part of Silicon Graphics’ commitment to deliver industry-leading application performance
through advanced technology, the OCTANE platform now incorporates both system
architectural improvements and a newgeneration MIPS microprocessor, R12000. This 



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