mosfet modelling research papers 2




An effective potential approach to modeling 25 nm MOSFET devices
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S Ahmed, C Ringhofer, D Vasileska ,Journal of computational electronics, 2010 ,Springer
Abstract We present a thermodynamic approach to introducing quantum corrections to the
classical transport picture in semiconductor device simulation. The approach leads to a
modified Boltzmann equation with an effective quantum potential. We study the quantum 

 MOSFET threshold voltage: definition, extraction, and applications
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MB Machado, OF Siebel, MC Schneider ,Proceedings of , 2011 ,209.250.82.216
Page 1. MOSFET Threshold Voltage: Definition, Extraction, and Applications Federal University
of Santa Catarina Brazil  7 The g ds /I D procedure 77 Direct determination of MOSFET parameters
from the I D vs V S curve at low V DS (linear region) D md S ms D Vg Vg I ? + ? ,= 

 Monte Carlo Simulation of Impact of Random Telegraph Noise in 45 nm MOSFET Due to Combined Effects of Random Interface Traps and Random Channel
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N Ashraf, D Vasileska, Z Ma ,Nanotech Conference and , 2010 ,materiales.azc.uam.mx
ABSTRACT This paper presents a 3-D Ensemble Monte Carlo (EMC) based simulation for
45 nm gate length MOSFET to account for the fluctuations in drain current (saturation) and
threshold voltage as causes of reliability failures integrating the effects of (1) statistical 

Characterization of MOSFET-like Carbon Nanotube Field Effect Transistor
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AM Hashim, HH Ping, CY Pin ,AIP Conference Proceedings, 2010 ,pdfserv.aip.org
The downscaling of metal-oxide-semiconductor field-effect transistor (MOSFET) has been
taking place since decades ago for enhancing circuit functionality and also for extending
Moore’s Law. As the downsizing of MOSFET continues, it faces the challenge of size 

Establishing a standard calibration methodology for MOSFET detectors in computed tomography dosimetry
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SL Brady, RA Kaufman ,Medical Physics, 2012 ,pdfserv.aip.org
Purpose: The use of metal-oxide-semiconductor field-effect transistor (MOSFET) detectors
for patient dosimetry has increased by~ 25% since 2005. Despite this increase, no standard
calibration methodology has been identified nor calibration uncertainty quantified for the 

 Optimized oxygen annealing process for Vth tuning of p-MOSFET with high-k/metal gate stacks
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T Kawanago, Y Lee, K Kakushima , Solid-State Device , 2010 ,iwailab.ep.titech.ac.jp
Abstract—A demonstration of VFB/Vth tuning has been conducted by optimized annealing in
oxygen ambient for direct contact of high-k with Si gate stacks. The amount of oxygen atoms
has been controlled by optimized annealing temperature and the thickness of the gate 

 Linearity Performance Assessment of Nanoscale Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET for RFIC design and Wireless
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P Malik, R Chaujar, M Gupta , conference and Expo , 2010 ,materiales.azc.uam.mx
ABSTRACT In this work, an extended study of linearity behaviour of proposed Gate Material
Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been performed
using ATLAS and DEVEDIT device simulators and the results so obtained are compared 

 High-Performance III-V MOSFET with Nano-stacked High-k Gate Dielectric and 3D Fin-shaped Structure.
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SH Chen, WS Liao, HC Yang, SJ Wang ,Nanoscale research , 2012 ,nanoscalereslett.com
Abstract A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V
metaloxide-semiconductor field-effect transistor (MOSFET) fabrication has been
demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped 

 Hybrid Evolutionary Algorithm in MOSFET parameter extraction
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J Arabas, S Szostak ,Prace Naukowe Politechniki , 2008 ,exact.ipipan.waw.pl
Abstract. In this paper we report an ongoing research on applying evolutionary computation
to the identification of technological parameters of MOS transistors (MOSFETs) using the
current-voltage measurements. The identification consists in approximating the observed 

 Interface Traps in Surface-Potential-Based MOSFET Models
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Z Chen, X Zhou, GH See, Z Zhu, G Zhu ,Proc. 2009 Nanotech Conf.(WCM- , 2009
 Printed 2009.04.27 Slide No.1/18 Interface Traps in Surface-Potential- Based MOSFET Models
Zuhui Chen, Xing Zhou, Guan Huei See, Zhaomin Zhu, and Guojun Zhu  Printed 2009.04.27 Slide
No.2/18 Interface Traps in Surface-Potential- Based MOSFET Models Outline 

 Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET
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CH Suh ,J. Semi. Tech. and Sci, 2011
Abstract—A two-dimensional analytical model for deriving the threshold voltage of a short
channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested.
By taking into account the lateral variation of the surface potential, introducing the natural 

 Gate Leakage Aware Optimal Design of Modified Hybrid Nanoscale MOSFET and Its Application to Logic Circuits
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AK Rana, N Chand, V Kapoor ,Iranian Journal of Electrical, 2011 ,64.130.220.45
Abstract: With the explosive growth in portable computing and wireless communication
during last few years, power dissipation has become critical issue. Under such condition
gate leakage has been recognized as a dominant component of power dissipation. This 

 Dosimetric Characteristics of Standard and Micro MOSFET Dosimeters as In-vivo Dosimeter for Clinical Electron Beam
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JB Chung, JW Lee, TS Suh, DH Lee ,Journal of the Korean , 2009
As in-vivo dosimetry is the most direct and independent method for monitoring the dose
delivered to patients, it is recommended by various national and international organizations.
In conventional radiotherapy, ionization chambers, radiographic films, and 

 A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design
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F Djeffal, A Ferdi, M Chahdi ,Lecture Notes in Engineering and Computer , 2012
Abstract—The Double Gate silicon (DG) MOSFET with extremely short-channel length has
the appropriate features to constitute the devices for nanoscale circuit design. To develop a
physical model for extremely scaled DG MOSFETs, the drain current in the channel must 

 Effect of Counter-doping Thickness on Double-gate MOSFET Characteristics
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T George James, S Joseph, V Mathew ,JOURNAL OF SEMICONDUCTOR , 2010
Abstract—This paper presents a study of the influence of variation of counter doping
thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short
channel effects are estimated from the computed values of current-voltage (IV) 

Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime
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AK Rana, N Chand, V Kapoor , Journal of Micro-Nano Scale Transport, 2010 ,Multi-Science
In this paper, an analytical model has been developed for gate tunneling current in nano
scale MOSFET with high-k dielectric stack as gate insulator. A computationally efficient
model for gate tunneling current through different high-k gate stack structure is presented. 

Inducing Chaos in MOSFET-Based Electronic Circuits
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Abstract We construct a nonlinear, MOSFET-based electronic circuit and address the
question of inducing chaos. A recently proposed method makes use of resonant
perturbations, which is applicable to situations where chaos is desired, under the 

 High-Voltage MOSFET compact modelling
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Low Voltage Part Main Physical and Electrical Parameters TOX 50· 10-9 08 Gate oxide
thickness. If TOX= 0 then COX is used. m COX 0.7· 10-3 08 Gate oxide capacitance per unit
area. F/m2 VFB-1.1-88 Flat-Band voltage at source end of channel. If VFB=-103 then 

 A Compact Gate Tunnel Current Model for Nano Scale MOSFET with Sub1nm Gate Oxide
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A Kumar, N Chand, V Kapoor ,International Journal of Applied , 2010 ,ipajournals.com
ABSTRACT As the CMOS devices are scaled down to nano domain and below in order to
take the advantage of higher density, high speed, lower cost etc, gate tunneling current
through gate oxide becomes important because of continued reduction of gate dielectric at 

 Theory of Bipolar MOSFET (BiFET) with Electrically Short Channels
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BB Jie, CT Sah ,Technical Proceedings of NSTI-Nanotech, 2010 ,materiales.azc.uam.mx
ABSTRACT Bipolar MOSFETs with a pure base and two MOS gates usually have electrically
short channels compared with its intrinsic Debye length of about 25µm at room
temperatures. This short channel effect was missed by all previous authors because they 

Subthreshold behavior optimization of nanoscale Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET using multi-objective genetic algorithms
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T Bendib, F Djeffal, D Arar ,Journal of computational electronics, 2011 ,Springer
Abstract In this paper, a multi-objective genetic algorithms-based approach is proposed to
study and optimize the subthreshold behavior of Graded Channel Gate Stack Double Gate
(GCGSDG) MOSFET for nanoscale CMOS digital applications. The subthreshold 

 Further EOT scaling below 0.4 nm for high-k gated MOSFET
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K Kakushima, K Okamoto, K Tachi ,Technical digest of , 2008 ,iwailab.ep.titech.ac.jp
Downsizing has been the most effective way to improve the performance of MOSFET [1]. For
gate oxide, the scaling limit has been resolved with the introduction of high-k, which enables
further reduction of the equivalent oxide thickness (EOT). However, it is expected that 

 Symmetric and asymmetric double gate MOSFET modeling
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H Abebe, E Cumberbatch, H Morris, V Tyree ,J. Semicond. Technol. , 2009
Abstract—An analytical compact model for the asym-metric lightly doped Double Gate (DG)
MOSFET is presented. The model is developed using the Lambert Function and a 2-
dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the 


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