vlsi research papers 2012-105


Minimization of Leakage Current in VLSI Design
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K Kaur, A Noor
Abstract-To meet the ever-increasing demand of high performance systems, more and more
functions are integrated into single chip by scaling down the size of device. Leakage current
is becoming an increasingly important fraction of total power dissipation of integrated 

 High ? Speed VLSI Architectures for Turbo Decoders
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Z Wang, X Huang ,cdn.intechopen.com
Turbo code, being one of the most attractive near Shannon limit error correction codes, has
attracted tremendous attention in both academia and industry since its invention in early
1990· s. In this chapter, we will discuss high speed VLSI architectures for Turbo decoders. 

 A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
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PS Bala, S Raghavendra
Abstract-In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC)
for high-speed arithmetic. By combining multiplication with accumulation and devising a
hybrid type of carry save adder (CSA), the performance was improved. Since the 

 FPGA Implementation of Efficient VLSI Architecture for Fixed Point 1-D DWT Using Lifting Scheme
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D Sowjanya, KNH Srinivas, PV Ganapathi ,International Journal
ABSTRACT In this paper, a scheme for the design of area efficient and high speed pipeline
VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using
lifting scheme is proposed. The main focus of the scheme is to reduce the number and 

 Low Power Glitch Free Modeling in Vlsi Circuitry Using Feedback Resistive Path Logic
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M ASHARANI, N CHANDRASEKHAR, RS RAO ,Editorial Board
Abstract Low power has emerged as a principal theme in today? s electronics industry. This
work focus on the development of low power VLSI design methodology on system level
modeling and circuit level modeling for power optimization. This work develops a power 

 VLSI and Fabrication
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A Dhawane, P Nichhal ,World Research Journal of Telecommunications , 2012
Abstract-Since the invention of the integrated circuit in 1988, the number of processing steps
required to make one has grown from Less than 10 to several hundreds. At the same time-,
the silicon wafers on which the VLSI ICs. are produced have gone from being coin sized to 

 Survey on VLSI Architecture for 2D DWT Using Lifting Scheme
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GS Ragavi, V Geetha
Abstract—In this paper, we review recent developments in VLSI architectures and algorithms
for efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic
principle behind the lifting based scheme is to decompose the finite impulse response ( 

 Towards biologically realistic multi-compartment neuron model emulation in analog VLSI
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Abstract. We present a new concept for multi-compartment emulation on neuromorphic
hardware based on the BrainScaleS wafer-scale system. The implementation features
complex dendrite routing capabilities, realistic scaling of compartmental parameters and 

 VLSI based Induction Motor Speed Control using Auto Tune PID controller
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Induction Motor Speed Control using Auto Tune PID controller. The present paper
suggested stand alone control device for industrial induction motor speed control. PID tuning
is proposed using successive approximation method with hardware and software 

 Successive Interference Cancellation for 3G Downlink: Algorithm and VLSI Architecture
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Abstract—This paper presents a VLSI implementation of an MMSE successive interference
cancellation multiuser detector (SIC-MUD) for the downlink of a TD-SCDMA system.
Computation in the frequency domain, group-wise interference cancellation, and pre- 

 Accurate Crosstalk Analysis for RLC On-Chip VLSI Interconnect
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Abstract—This work proposes an accurate crosstalk noise estimation method in the
presence of multiple RLC lines for the use in design automation tools. This method correctly
models the loading effects of non switching aggressors and aggressor tree branches 

 A GENETIC ALGORITHM FOR VLSI FLOOR PLANNING
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CD Rawat, A Shahani, N Natu, A Badami, R Hingorani ,ijesat.com
Abstract The classical floor planning techniques use block packing to minimize chip area, by
making use of algorithms like B-TREE representation, simulated annealing. To get an
optimal solution it is imperative to choose an efficient, cost effective algorithm. This paper 

 CROSSTALK NOISE AND DELAY REDUCTION IN VLSI INTERCONNECTS
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C Mohali ,ijater.com
Abstract Crosstalk in interconnects had a great impact on overall reliability and performance
of IC and thus it plays a key role in deep submicron (DSM) VLSI circuits. In this paper schmitt
trigger is designed as a buffer which operates at a 20 GHz frequency so as to minimize 

 A Review on Channel Routing On VLSI Physical Design
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AK Khan, B Das, TK Bayen ,iosrjournals.org
Abstract: We know that channel routing is very important problem in VLSI physical design.
The main objective of a channel routing algorithm is the reduction of the area of a IC chip. In
this paper, we just do a survey on some impotent multi-layer routing algorithms. Here we 

 Effect of Equal and Mismatched Signal Transition Time on Power Dissipation in Global VLSIInterconnects
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DK Sharma, BK Kaushik, RK Sharma ,International Journal
ABSTRACT High density chips have introduced problems like crosstalk noise and power
dissipation. The mismatching in transition time of the inputs occurs because different lengths
of interconnects lead to different parasitic values. This paper presents the analysis of the 

 Carbon Nanotube-and Graphene Based Devices, Circuits and Sensors for VLSI Design
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With the reduction in power consumption and size chip, the electronic industry has been
searching novel strategies to overcome these constraints with an optimal performance.
Carbon nanotubes (CNTs) due to their extremely desirable electrical and thermal 

 Study, Implementation and Survey of Different VLSI Architectures for Multipliers
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S Kandalgaonkar, KR Rasane
Abstract—Multiplication is the most useful operation required in many hardware
computations. Efficient implementation of multipliers is required in many applications. This
paper is a survey of different architectures for multipliers such as Array Multiplier using 

 VLSI Implementation of Approximate Message Passing for Signal Restoration and Compressive Sensing
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Abstract—Sparse signal recovery finds use in a variety of practical applications, such as
signal and image restoration and the recovery of signals acquired by compressive sensing.
In this paper, we present two generic VLSI architectures that implement the approximate 

 Algorithms for CAD Tools VLSI Design
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KAS Devi ,cdn.intechweb.org
Due to advent of Very Large Scale Integration (VLSI), mainly due to rapid advances in
integration technologies the electronics industry has achieved a phenomenal growth over
the last two decades. Various applications of VLSI circuits in high-performance computing, ..







vlsi research papers 2012-105 IEEE PAPER

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  • Viviana

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