vlsi research papers 2012-104


A Survey of Various Algorithms for Vlsi Physical Design
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R Rajine Swetha, BS Babu, SD KA
Abstract—Electronic Systems are the core of everyday lives. They form an integral part in
financial networks, mass transit, telephone systems, power plants and personal computers.
Electronic systems are increasingly based on complex VLSI (Very Large Scale Integration 

 R-2R Ladder D/A Converter Circuit Performance Optimization for Mixed-Signal VLSI Chips via Generalized Geometric Programming
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J Chakraborty, K Das, SK Datta, P De, A Acharyya
Abstract—In this paper the critical delay in R-2R Ladder digital to analog (D/A) converter
circuits is minimized by uniform interconnect wire sizing via Generalized Geometric
Programming approach. Elmore delay model is considered for calculating the delays 

 Photolithographic Techniques for LSI and VLSI
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MG Wani, VN Gohokar
1 INTRODUCTION ecent progress in electronics has been mainly in semiconductor
technology particularly in the field of silicon technology. Here LSI stands for large scale
integration and VLSI for very large scale integration. These techniques are usually used 

 Analysis of Floorplanning Algorithms in VLSI Physical Designs
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D Batra ,ijater.com
Abstract The first step in the Physical Design flow is Floorplanning. The floorplanning stage
ensures that (1) every chip module is assigned a shape and a location, so as to facilitate
gate placement, and (2) every pin that has an external connection is assigned a location, 

 Design and Low Power VLSI Implementation of Triple-DES Algorithm
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A Camacho, I Sanchez, EB John, R Krishnan ,engineering.utsa.edu
Abstract—Triple DES (Data Encryption Standard) is a widely used encryption algorithm
known to achieve good performance and high security. In this paper, we describe the design
and low power VLSI implementation of the well-known triple DES algorithm. The 

 Design Rules in VLSI Routing
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C Schulte ,hss.ulb.uni-bonn.de
VLSI1 design is the process of creating the logical and physical representation of highly
integrated circuits, which consist of millions of transistors. Because most underlying
mathematical problems are extremely hard, and instance sizes occurring in practice are 

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T Muthumanickam, A Nagappan, T Sheela ,ijcnwc.org
Abstract—Cryptographic algorithms are more efficiently implemented in custom hardware
than in software running on general-purpose processors. The hardware implementation
approaches for the AES (Advanced Encryption Standard) Algorithm describes the design 

 Closed form Delay Model for on-Chip VLSI RLCG Interconnects for Ramp Input for Different Damping Conditions
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Abstract—Fast delay estimation methods, as opposed to simulation techniques, are needed
for incremental performance driven layout synthesis. On-chip inductive effects are becoming
predominant in deep submicron interconnects due to increasing clock speed and circuit 

 VLSI Implementation of DWT Using Systolic Array Architecture
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MN Kumar, J Hemanth, KD Prasad
Abstract—This work presents an implementation of Discrete Wavelet Transform (DWT) using
Systolic architecture in VLSI. This architecture consist of Input delay unit, filter, register bank
and control unit. This performs the calculation of high pass and low pass coefficients by 

 VLSI Implementation of Fast Convolution Based 2-D Discrete Wavelet Transform for High Speed, Area Efficient Image Computing
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C Ramachandran, TRD Kumar ,ijcns.com
Abstract A VLSI design approach of a high speed and real-time 2-D Discrete Wavelet
Transform computing is being presented in the paper. The proposed architecture, based on
new and fast convolution approach, reduces the hardware complexity in addition to 

 An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing
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MAJ Chowdhury, MS Rizwan, MS Islam
Abstract—In CMOS integrated circuit design there is a trade-off between static power
consumption and technology scaling. Recently, the power density has increased due to
combination of higher clock speeds, greater functional integration, and smaller process 

 VLSI Implementation of Serial-Serial Multiplier based on Asynchronous Counter Accumulation
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YAB Francis
Abstract—Multipliers are the fundamental and essential building blocks of VLSI systems.
The design and implementation approaches of multipliers contribute substantially to the
area, speed and power consumption of computation intensive VLSI system. The objective 

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C BRANTLEY ,2012 ,xplorestaging.ieee.org
The Circuits and Systems Society is an association of IEEE members with professional
interest in the field of circuits and systems theory. All members of the IEEE are eligible for
membership in the Circuits and Systems Society upon payment of the annual Society 

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S Tembhurne, LP Thakare ,International , 2012 ,journalofcomputerscience.com
Abstract Multiplier is an important block of wireless communication system. In many
applications there is a need to mix the signals of different frequencies or signals of different
types, which emphasises the use of mixers or multipliers for different RF applications. 

 VLSI Implementation of a 2×2 MIMO-OFDM System on FPGA
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R Premalatha, M Shanthi
Abstract—Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-
OFDM) technology is an attractive transmission technique for wireless communication
systems with multiple antennas at transmitter and receiver. The core of this technology is