N-Model Tests for VLSI Circuits
We define N-model tests that target detection of faults belonging to N specified fault models. We pro- vide a method for deriving minimal tests using integer linear programming (ILP) without reducing the indi- vidual fault model coverage. Any test sequences, de- terministic, random, functional, N-detect, etc., can be minimized for the given set of fault […]
Reordering of Test Vector Using Artificial Intelligence Approach for Power Reduction during VLSI Testing
Optimization of testing power is a major significant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as […]
Distributed Page Ranking in Structured P2P Networks
This paper discusses the techniques of performing distributed page ranking on top of structured peer-to-peer networks. Distributed page ranking are needed because the size of the web grows at a remarkable speed and centralized page ranking is not scalable. Open System PageRank is presented in this paper based on the traditional PageRank used by Google. […]