N-Model Tests for VLSI Circuits

We define N-model tests that target detection of faults belonging to N specified fault models. We pro- vide a method for deriving minimal tests using integer linear programming (ILP) without reducing the indi- vidual fault model coverage. Any test sequences, de- terministic, random, functional, N-detect, etc., can be minimized for the given set of fault models. Stuck-at, transition, and pseudo stuck-at IDDQ faults are used as illustrations. We generate tests using Mentor Graphics FastScan ATPG tool employing a single fault model at a time. A minimized test set for the three fault mod- els is then obtained by solving the proposed combined ILP problem. For s5378 benchmark circuit we achieved about 50% reduction in the number of vectors and 10% reduction in the IDDQ current measurements compared to the originally generated tests. We also propose a reduced complexity ILP approximation.

Several years ago, in the published results of a Se- matech study , four types of tests, namely, scan- based stuck-at, scan-based delay, IDDQ, and functional, were examined. A general conclusion was that none of the tests could be dropped. That study has been a sub- ject for numerous discussions. With advances in technology, new fault modes are continuously emerging and the gap between the age-old stuck-at fault model and \realistic defects” continues to widen. On the other hand, the need to minimize test length and test time has never been greater because of complex system-on- chip (SOC) devices. This paper addresses the problem of combining tests that target several fault models into a single compact test. Test minimization has been a widely researched area. However, most of the published methods will be di- cult to apply to multiple fault models. Integer linear programming (ILP) is an e ective method of test op- timization. Applications of ILP have been reported for separately optimizing vectors for detection of single stuck-at faults , N-detection of single stuck-at faults [3], and detection of transition faults . To our knowledge a simultaneous ILP optimization for multi- ple fault models has not been attempted before. In this paper we develop an ILP method for multiple- fault models. It is recognized that the complexity of ILP would be too high even for medium size circuits. This problem is overcome by using reduced-complexity ILP variations. We show that such procedures can ef- fectively solve the test minimization problem. In Section 3, we define a new type of test, the N- model test. For these tests the target faults belong to several selected fault models. The rest of the paper develops procedures for generating and optimizing N- model tests using the existing ATPG tools.

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